On discretization of delays in timed automata and digital circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1466, Issue , 1998, Pages 470-484

  Asarin, Eugene ^a   Maler, Oded ^b   Pnueli, Amir ^c  

^a INSTITUTE FOR INFORMATION TRANSMISSION PROBLEMS   (Russian Federation)

^b VERIMAG   (France)

^c WEIZMANN INSTITUTE OF SCIENCE   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; TIMING CIRCUITS;

CYCLIC CIRCUITS; DENSE-TIME; DISCRETIZATIONS; FOLLOWING PROBLEM; QUALITATIVE BEHAVIOR; SIMPLE CIRCUITS; TIMED AUTOMATA; VERIFICATION RESULTS;

DELAY CIRCUITS;

EID: 84945940816     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0055642     Document Type: Conference Paper

References (16)

1. R. Alur, C. Courcoubetis, and D.L. Dill, Model Checking in Dense Real Time, Information and Computation 104, 2-34, 1993.
2. R. Alur and D.L. Dill. A theory of timed automata, Theoretical Computer Science, 126, 183-235, 1994.
3. E. Asarin, M. Bozga, A. Kerbrat, O. Maler, A. Pnueli and A. Rasse, Data-Structures for the Verification of Timed Automata, in O. Maler (Ed.), Proc. HART’97, LNCS 1201, 346-360, Springer, 1997.
4. M. Bozga and O. Maler, Modeling and Verification of the STARI Chip using Timed Automata, submitted, 1998.
5. M. Bozga, O. Maler, A. Pnueli and S. Yovine, Some Progress in the Symbolic Verification of Timed Automata, in O. Grumberg (Ed.) Proc. CAV’97, 179-190, LNCS 1254, Springer, 1997.
6. J.A. Brzozowski and C-J.H. Seger, Asynchronous Circuits, Springer, 1994.
7. C. Daws, A. Olivero, S. Tripakis, and S. Yovine, The Tool KRONOS, in R. Alur, T.A. Henzinger and E. Sontag (Eds.), Hybrid Systems III, LNCS 1066, 208-219, Springer, 1996.
8. D.L. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in J. Sifakis (Ed.), Automatic Verification Methods for Finite State Systems, LNCS 407, 197-212, Springer, 1989.
9. T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine, Symbolic Model-checking for Real-time Systems, Information and Computation 111, 193-44, 1994.
10. H.R. Lewis, A logic of concrete time intevrals, Proc. LICS’90, IEEE, 1990.
11. A. Göllü, A. Puri and P. Varaiya, Discretization of Timed Automata, Proc. 33rd CDC, 1994.
12. T. Henzinger, Z. Manna, and A. Pnueli. What Good are Digital Clocks?, in W. Kuich (Ed.), Proc. ICALP’92, LNCS 623, 545-558, Springer, 1992.
13. O. Maler and A. Pnueli, Timing Analysis of Asynchronous Circuits using Timed Automata, in P.E. Camurati, H. Eveking (Eds.), Proc. CHARME’95, LNCS 987, 189-205, Springer, 1995.
14. O. Maler and S. Yovine, Hardware Timing Verification using KRONOS, In Proc. 7th Israeli Conference on Computer Systems and Software Engineering, Herzliya, Israel, June 1996.
15. A. Rabinovich and B.A. Trakhtenbrot, From finite automata toward hybrid systems, Proc. FCT’97, 1997.
16. S. Tasiran and R.K. Brayton, STARI: A Case Study in Compositional and Hierarchical Timing Verification, in O. Grumberg (Ed.) Proc. CAV’97, 191-201, LNCS 1254, Springer, 1997.