A Statistical Gate-Delay Model Considering Intra-Gate Variability

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 908-913

  Okada, Kenichi ^a   Yamaoka, Kento ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MOS DEVICES; SENSITIVITY ANALYSIS; STATISTICAL METHODS;

GATE DELAYS; SUBMICRON TECHNOLOGY;

GATES (TRANSISTOR);

EID: 0346778705     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159782     Document Type: Conference Paper

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