Up-to-50-GHz-clock InP DHBT digital IC's and optical system experiments

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 2003, Pages 173-176

  Godin, J ^a   Riet, M ^a   Blayac, S ^a   Berdaguer, P ^a   Dhalluin, V ^a   Kahn, M ^a   Kasbari, A ^a,c   Puyal, V ^b   Moulu, J ^a   Jorge, F ^a   Vuye, S ^a   Giraudet, L ^a,d   Franz, B ^a   Konczykowska, A ^a  

^a NOKIA RESEARCH CENTER   (United States)

^b LIRMM   (France)

^c ENSEA   (France)

^d ORANGE LABS   (France)

Author keywords

HBT; InP; OC 768

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DENSE WAVELENGTH DIVISION MULTIPLEXING; FIBER OPTIC NETWORKS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; OPTICAL COMMUNICATION; OPTICAL SYSTEMS; OPTIMIZATION; SEMICONDUCTING INDIUM PHOSPHIDE; SIGNAL PROCESSING; TIME DIVISION MULTIPLEXING;

LARGE SIGNAL SIMULATION; OPTICAL NETWORKS;

DIGITAL INTEGRATED CIRCUITS;

EID: 0346305126     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/gaas.2003.1252388     Document Type: Conference Paper

References (13)

1. H. Bulow, "Electronic equalization of transmission impairments", OFC 2002, paper TuE4, pp. 24-25, Mar 2002
2. D. Streit, et al., "InP HEMT and HBT applications beyond 200 GHz", IPRM '02, pp. 11-14, May 2002
3. J. Godin, et al., "InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits", GaAs IC'02, pp. 215-218, Oct. 2002
4. S. Blayac, et al., "MSI InP/InGaAs DHBT technology: beyond 40 Gbit/s circuits", IPRM '02, pp. 51-54, May 2002
5. P. Asbeck, "III-V HBTs for Microwave Applications: Technology Status and Modeling Challenges", BCTM 2000, pp. 52-57, Sept. 2000 (see also UCSD HBT description athttp://hbt.ucsd.edu)
6. A. Kasbari, et al., "Design of high-speed master-slave D-type flip-flop in InP DHBT technology", IEEE Trans. on MTT, Vol. 50, Iss. 12, pp. 3064-3069, Dec. 2002
7. A. Konczykowska, et al., "High-sensitivity decision circuit in InP/InGaAs DHBT technology and 40-80 Gbit/s optical experiments", submitted to IEE Electronics Letters.
8. G. Wanlin, et al., "High responsivity side illuminated AlGaInAs PIN photodiode for 40 Gbit/s-40 GHz applications", ECOC '97, Vol. 2, pp. 37-40, Sept. 97
9. W. Idler, et al., "System Performance and Tolerances of 43 Gbit/s ASK and DPSK modulation formats", ECOC '03, paper Th2.6.3, Sept. 2003
10. A. Konczykowska, et al., "High quality 80Gbit/s InP DHBT selector and its use for NRZ-RZ conversion", IEE Electronics Letters, Vol. 39, No. 1, pp. 49-51, Jan. 2003
11. H. Bissessur, et al., "3.2 Tbit/s (80 × 40 Gbit/s) phase-shaped binary transmission over 100 km with 0.8 bit/s/Hz efficiency", IEE Electronics Letters, Vol. 38, No 8, pp. 377-379, 11 Apr 2002.
12. H. Bissessur, et al., "1.6 Tbit/s (40 × 40 Gbit/s) DPSK transmission over 3 × 100 km of TeraLight fibre with direct detection", IEE Electronics Letters, Vol. 39, No. 2, pp. 192-192, 23 Jan 2003
13. F. Buchail et al., "Adaptive 1 and 2 Stage PMD-Compensators for 40 Gbit/s Transmission Using Eye Monitor Feedback", OFC '03, Paper Tu04, Vol. 1, pp. 262-263, March 2003