InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 2002, Pages 215-218

  Godin, Jean ^a   Riet, M ^a   Blayac, S ^a   Berdaguer, P ^a   Dhalluin, V ^a   Alexandre, F ^a   Kahn, M ^a   Pinquier, A ^a   Kasbari, A ^a   Moulu, J ^a   Konczykowska, A ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DENSE WAVELENGTH DIVISION MULTIPLEXING; ELECTRONIC EQUIPMENT; FLIP FLOP CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; OPTICAL COMMUNICATION; POLYIMIDES; TRANSMITTERS;

COMMUNICATION CIRCUITS;

SEMICONDUCTING INDIUM COMPOUNDS;

EID: 0036442077     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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9. J. Godin, R. Lefèvre, "Design of Decision and Driver Circuits for 40 Gbit/s Data Rate Optical Communications", in Proc. IMS '2001, Phoenix (USA), 21 May 2001-Workshop WMC.
10. th June 2002, pp. 557-558.
11. F. Buchali et al., "Fast eye monitor for 10 Gbit/s and its application for optical PMD compensation", in Techn. Digest OFC '01, Anaheim (USA), 17-22 March 2001, paper TuP5.