Design of high-speed master-slave D-type flip-flop in InP DHBT technology

IEEE Transactions on Microwave Theory and Techniques

Volumn 50, Issue 12, 2002, Pages 3064-3069

  Kasbari, Abed Elhak ^a   André, Philippe ^b,c   Konczykowska, Agnieszka ^b   Riet, Muriel ^b   Blayac, Sylvain ^b   Ouslimani, Habiba ^a   Godin, Jean ^b  

^a TELECOM PARISTECH   (France)

^b OPTO+   (France)

^c ON SEMICONDUCTOR   (United States)

Author keywords

Bipolar integrated circuits; Flip flops; Indium compounds; SONET; Very high speed integrated circuits

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; BIT ERROR RATE; COMMUNICATION; INDIUM COMPOUNDS; OPTICAL FIBERS;

HIGH SPEED INTEGRATED CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 0036904718     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2002.805290     Document Type: Conference Paper

References (13)

1. K. Fukuchi, "Wideband and ultra-dense WDM transmission technologies toward over 10-Tb/s capacity," in Opt. Fiber Conf., Anaheim, CA, Mar. 2002, Paper ThX5, pp. 558-559.
2. S. Bigo et al., "Transmission of 125 WDM channels at 42.7 Gbits/s (5 Tbit/s capacity) over 12 × 100 km of teralight TM ultra fiber," in Proc. Eur. Opt. Commun. Conf., Amsterdam, The Netherlands, Sept. 2001.
3. B. Wedding et al., "SiGe circuits for high bit-rate optical communications systems," in Proc. Int. Circuits Syst. Symp., vol. II, Orlando, FL, June 1999, pp. 492-495.
4. Y. Kuriyama, T. Sugiyama, S. Hongo, J. Akagi, K. Tsuda, N. Iizuka, and M. Obara, "A 40 GHz D-type flip-flop using AlGaAs/GaAs HBT's," in Proc. GaAs IC Symp., Philadelphia, PA, 1994, pp. 189-192.
5. L. Samoska, R. Pullela, B. Agarwal, D. Mensa, Q. Lee, V. Kaman, J.Guthrie, and M. Rodwell, "InP heterojunction bipolar transistor decision circuits," in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Baltimore, MD, 1998, pp. 1843-1846.
6. E. Sano, H. Nakajima, N. Watanabe, and S. Yamahata, "40 Gbit/s decision IC using InP/InGaAs composite-collector heterojunction bipolar transistors," Electron. Lett., vol. 35, no. 14, pp. 1194-1195, July 1999.
7. K. Murata, T. Otsuji, and Y. Yamane, "45 Gbit/s decision IC module using InAlAs/InGaAs/InP HEMT's," Electron. Lett., vol. 35, no. 16, pp. 1379-1380, Aug. 1999.
8. S. Blayac et al., "Lateral design of InP/InGaAs DHBT's for 40 Gbit/s IC's," in Proc. Indium Phosphide and Related Mater., Williamsburg, VI, May 2000, pp. 481-484.
9. _, "MSI InP/InGaAs DHBT technology: Beyond 40 Gbit/s circuits," in Proc. Indium Phosphide and Related Mater., Stockholm, Sweden, May 2002, pp. 51-54.
10. N. Kauffmann, S. Blayac, M. Abboun, R. André, F. Aniel, M. Riet, J.-L. Benchimol, J. Godin, and A. Konczykowska, "InP HBT driver circuit optimization for high-speed ETDM transmission," IEEE J. Solid-State Circuits, vol 36, pp. 639-647, Apr. 2001.
11. R. Schmid, T.-F. Meister, M. Rest, and H.-M. Rein, "SiGe driver circuit with high output amplitude operating up to 23 Gb/s," IEEE J. Solid-State Circuits, vol. 34, pp. 886-891, June 1999.
12. J. Hauenschild et al., "Influence of transmission-line interconnections between Gigabit-per-second IC's on time jitter and instabilities," IEEE J. Solid-State Circuits, vol. 25, pp. 763-766, June 1990.
13. N. Kauffmann and A. Konczykowska, "Interconnect layout modeling and simulation in high speed circuits," in Proc. Int. Circuits Syst. Symp., Geneva, Switzerland, May 2000, pp. III 125-128.