High-sensitivity decision circuit in InP/InGaAs DHBT technology and 40-80 Gbit/s optical experiments

Electronics Letters

Volumn 39, Issue 21, 2003, Pages 1532-1533

  Konczykowska, A ^a   Jorge, F ^a   Kasbari, A ^a   Idler, W ^b   Giraudet, L ^a   Schuh, K ^b   Junginger, B ^b   Godin, J ^a  

^a OPTO+   (France)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ELECTRIC BREAKDOWN; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; OPTICAL COMMUNICATION EQUIPMENT; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SIGNAL RECEIVERS;

D FLIP-FLOPS; DECISION CIRCUIT SENSITIVITY; DOUBLE HETEROSTRUCTURE BIPOLAR TRANSISTOR; OPTICAL RECEIVER;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0142216604     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030941     Document Type: Article

References (3)

1. Ishii, K., et al.: 'High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs', Electron. Lett., 2002, 38, (12), pp. 557-558
2. Vetury, R., et al.: 'High sensitivity and wide-dynamic-range optical receiver for 40 Gbit/s optical communication networks', Electron. Lett., 2003, 39, (1), pp. 91-92
3. Blayac, S., et al.: 'MSI InP/InGaAs DHBT technology: beyond 40 Gbit/s circuits'. 14th Indium Phosphide and Related Materials Conference, in Proc. IPRM 2002, Stockholm, Sweden, B1-4, pp. 51-54