Introduction to generalized symbolic trajectory evaluation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 360-365

  Yang, J ^a   Seger, C J H ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT;

SYMBOLIC TRAJECTORY EVALUATION (STE);

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0035186885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A methodology for large-scale hardware verification
2. Combining theorem proving and trajectory evaluation in an industrial environment
3. Formally verifying a microprocessor using symbolic simulation methodology
4. Formal verification of digital circuits using symbolic ternary system models
5. The mathematical foundation of symbolic trajectory evaluation
6. A simple theorem prover based on symbolic trajectory evaluation and OBDDs
7. Formally verifying ieee compliance of floating-point hardware
8. Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
9. Formal verification of PowerPC(TM) arrays using symbolic trajectory evaluation
10. Formal verification of content addressable memories using symbolic trajectory evaluation
11. Formal verification by symbolic evaluation of partially-ordered trajectories
12. Generalized symbolic trajectory evaluation