Formal verification of a superscalar execution unit

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 161-166

  Nelson, Kyle L ^a   Jain, Alok ^a   Bryant, Randal E ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACES (COMPUTER); NETWORK PROTOCOLS; SIMULATION; SPECIFICATIONS; STANDARDS; SYSTEMS ANALYSIS;

SUBSYSTEM VERIFICATION; SYMBOLIC TRAJECTORY EVALUATION;

MICROPROCESSOR CHIPS;

EID: 0030703041     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266055     Document Type: Conference Paper

References (13)