Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2000, Pages 71-76

  Jahanpour, M S ^a   Cerny, E ^a  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

Asynchronous transfer mode; Automata; Clocks; Emulation; Engines; Hardware design languages; Mechanical factors; Protocols; Pulse generation; Switches

Indexed keywords

CLOCKS; ENGINES; MODEL CHECKING; NETWORK PROTOCOLS; PULSE GENERATORS; SWITCHES;

AUTOMATA; EMULATION; HARDWARE DESIGN LANGUAGE; MECHANICAL FACTORS; PULSE GENERATION;

ASYNCHRONOUS TRANSFER MODE;

EID: 84949676937     PISSN: 15526674     EISSN: None     Source Type: Journal    
DOI: 10.1109/HLDVT.2000.889562     Document Type: Article

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