Predicting the phase noise and jitter of PLL-based frequency synthesizers

Phase-Locking in High-Performance Systems: From Devices to Architectures

Volumn , Issue , 2003, Pages 46-69

  Kundert, Kenneth S ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Frequency synthesizers; Integrated circuit modeling; Jitter; Phase locked loops; Phase noise; Predictive models

Indexed keywords

FREQUENCY SYNTHESIZERS; JITTER; PHASE LOCKED LOOPS;

INTEGRATED CIRCUIT MODELING; NOISE BEHAVIOR; PREDICTIVE MODELS; RF SIMULATION; TRANSISTOR LEVEL;

PHASE NOISE;

EID: 84906846102     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545492.ch5     Document Type: Chapter

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