Time-resolved emission testing challenges for low voltage CMOS technologies

Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS

Volumn 2, Issue , 2003, Pages 596-597

  Song, Peilin ^a   Stellari, Franco ^a   Mc Manus, Moyra K ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; QUANTUM EFFICIENCY; VLSI CIRCUITS;

TIME RESOLVED EMISSION DIAGNOSTICS; TIME RESOLVED EMISSION TESTING;

CMOS INTEGRATED CIRCUITS;

CHIP DESIGN; CMOS TECHNOLOGY; EMISSION DIAGNOSTICS; EMISSION TESTING; LOW VOLTAGE CMOS TECHNOLOGY; TIME-RESOLVED EMISSIONS; TOOLING DESIGN;

EID: 0344897650     PISSN: 10928081     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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