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Volumn 19, Issue 9, 2000, Pages 1086-1092

On synchronizable circuits and their synchronizing sequences

Author keywords

[No Author keywords available]

Indexed keywords

STATE DIAGRAMS;

EID: 0034258899     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.863649     Document Type: Article
Times cited : (5)

References (18)
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    • Fault simulation for synchronous sequential circuits under the multiple observation time testing approach
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    • (1993) , pp. 292-300
    • Pomeranz, I.1    Reddy, S.M.2
  • 5
    • 0342342545 scopus 로고
    • A hybrid fault simulator for synchronous sequential circuits
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    • (1994) , pp. 614-623
    • Krieger, R.1    Becker, B.2    Keim, M.3
  • 6
    • 0031680074 scopus 로고    scopus 로고
    • MIX : A test generation system for synchronous sequential circuits
    • X. Lin I. Pomeranz S. M. Reddy MIX: A test generation system for synchronous sequential circuits Proc. 1998 VLSI Design Conf. 456 463 Proc. 1998 VLSI Design Conf. 1998-Jan. 5220 14112 646649
    • (1998) , pp. 456-463
    • Lin, X.1    Pomeranz, I.2    Reddy, S.M.3
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    • 85177126671 scopus 로고    scopus 로고
    • I. Pomeranz S. M. Reddy On removing redundancies from synchronous sequential circuits with synchronizing sequences IEEE Trans. Comput. 20 32 Jan. 1996 12 10292 481483
    • (1996) , pp. 20-32
    • Pomeranz, I.1    Reddy, S.M.2
  • 8
    • 0003694163 scopus 로고
    • Digital Systems Testing and Testable Design
    • Computer Science Press
    • M. Abramovici M. A. Breuer A. D. Friedman Digital Systems Testing and Testable Design 1990 Computer Science Press
    • (1990)
    • Abramovici, M.1    Breuer, M.A.2    Friedman, A.D.3
  • 9
    • 85177118717 scopus 로고
    • K.-T. Cheng V. D. Agrawal Initializability consideration in sequential machine synthesis IEEE Trans. Comput. 374 379 Mar. 1992 12 3571 127453
    • (1992) , pp. 374-379
    • Cheng, K.-T.1    Agrawal, V.D.2
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    • Minimum length synchronizing sequences of finite state machine
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    • (1993) , pp. 463-468
    • Rho, J.-K.1    Somenzi, F.2    Pixley, C.3
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    • On the initialization of sequential circuits
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    • Wehbeh, J.A.1    Saab, D.G.2
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    • M. Soufi Y. Savaria F. Darlay B. Kaminska Producing reliable initialization and test of sequential circuits with pseudorandom vectors IEEE Trans. Comput. 1251 1256 Oct. 1995 12 9844 467701
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    • Soufi, M.1    Savaria, Y.2    Darlay, F.3    Kaminska, B.4
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    • Synchronization of large sequential circuits by partial reset
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    • Lu, Y.1    Pomeranz, I.2
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.