A unified approach to topology generation and optimal sizing of floorplans

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 2, 1998, Pages 126-135

  Dasgupta, Partha S ^a   Sur Kolay, Susmita ^a   Bhattacharya, Bhargab B ^b  

^a INDIAN INSTITUTE OF MANAGEMENT CALCUTTA   (India)

^b JADAVPUR UNIVERSITY   (India)

Author keywords

And or graph search; Ao* algorithm; Heuristic search; Nonslicible; Vlsi floorplanning

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; GRAPH THEORY; HEURISTIC METHODS; LOGIC GATES; OPTIMIZATION; VLSI CIRCUITS;

FLOORPLANNING; HEURISTIC SEARCH; OPTIMAL SIZING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032003077     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.681262     Document Type: Article

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