Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors

Solid State Technology

Volumn 43, Issue 7, 2000, Pages 116-131

  Fritze, Michael ^a   Astotfi, David K ^b   Yost, Donna Ruth W ^a   Wyatt, Peter W ^b   Lhl, Hua Vu ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DRY ETCHING; LITHOGRAPHY; MASKS; PLASMA APPLICATIONS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY;

CHROMELESS PHASE SHIFT MASKS; HIGH DENSITY PLASMA ETCH PROCESS; WAFER FABRICATION;

TRANSISTORS;

EID: 0343006729     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

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1. The Lincoln Lab portion of this work was sponsored by the Defense Advanced Research Projects Agency under Air Force Contract #F19628-95C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the US government.
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