-
1
-
-
0030716608
-
Datascalar architectures
-
Denver, CO
-
D. Burger, S. Kaxiras, J.R. Goodman, Datascalar architectures, in: Proceedings of the ISCA 24, Denver, CO, 1997, pp. 338-349.
-
(1997)
In: Proceedings of the ISCA 24
, pp. 38-349
-
-
Burger, D.1
Kaxiras, S.2
Goodman, J.R.3
-
2
-
-
0343207157
-
Specialization: A way of life
-
Burgess B. Specialization: a way of life. Computer. 31:1998;43.
-
(1998)
Computer
, vol.31
, pp. 43
-
-
Burgess, B.1
-
3
-
-
0002766589
-
Preliminary discussion of the logical design of an electronic computing instrument
-
Reprint in: W. Aspray, A.P. Burks (Eds.), Papers of John von Neumann, MIT Press, Cambridge, MA
-
A.P. Burks, H.H. Goldstine, J. von Neumann, Preliminary discussion of the logical design of an electronic computing instrument. Report to the US Army Ordnance Department, 1946. Reprint in: W. Aspray, A.P. Burks (Eds.), Papers of John von Neumann, MIT Press, Cambridge, MA, 1987, pp. 97-146.
-
(1946)
Report to the US Army Ordnance Department
, pp. 97-146
-
-
Burks, A.P.1
Goldstine, H.H.2
Von Neumann, J.3
-
4
-
-
0031594025
-
Memory dependence prediction using store sets
-
Barcelona, Spain
-
G.Z. Chrysos, J.S. Emer, Memory dependence prediction using store sets, in: Proceedings of the ISCA 25, Barcelona, Spain, 1998, pp. 142-153.
-
(1998)
In: Proceedings of the ISCA 25
, pp. 142-153
-
-
Chrysos, G.Z.1
Emer, J.S.2
-
5
-
-
0343642752
-
Maintaining a leading position
-
Colwell R.P. Maintaining a leading position. Computer. 31:1998;45-47.
-
(1998)
Computer
, vol.31
, pp. 45-47
-
-
Colwell, R.P.1
-
6
-
-
0031274906
-
Direct rambus technology: The new main memory standard
-
Crisp R. Direct rambus technology: the new main memory standard. IEEE Micro. 17:1997;18-28.
-
(1997)
IEEE Micro
, vol.17
, pp. 18-28
-
-
Crisp, R.1
-
7
-
-
0032123777
-
The IA-64 architecture at work
-
Dulong C. The IA-64 architecture at work. Computer. 31:1998;24-31.
-
(1998)
Computer
, vol.31
, pp. 24-31
-
-
Dulong, C.1
-
8
-
-
0029666656
-
Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches
-
Philadelphia, PA
-
M. Evers, P.-Y. Chang, Y.N. Patt, Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches, in: Proceedings of the ISCA 23, Philadelphia, PA, 1996, pp. 3-11.
-
(1996)
In: Proceedings of the ISCA 23
, pp. 3-11
-
-
Evers, M.1
Chang, P.-Y.2
Patt, Y.N.3
-
10
-
-
0031594001
-
The effect of instruction fetch bandwidth on value prediction
-
Barcelona, Spain
-
F. Gabbay, A. Mendelson, The effect of instruction fetch bandwidth on value prediction, in: Proceedings of the ISCA 25, Barcelona, Spain, 1998, pp. 272-281.
-
(1998)
In: Proceedings of the ISCA 25
, pp. 272-281
-
-
Gabbay, F.1
Mendelson, A.2
-
11
-
-
0031270746
-
High-performance, open-standard memory
-
Gillingham P., Vogley B. High-performance, open-standard memory. IEEE Micro. 17:1997;29-39.
-
(1997)
IEEE Micro
, vol.17
, pp. 29-39
-
-
Gillingham, P.1
Vogley, B.2
-
12
-
-
0009616533
-
Reining in complexity
-
Grohoski G. Reining in complexity. Computer. 31:1998;41-42.
-
(1998)
Computer
, vol.31
, pp. 41-42
-
-
Grohoski, G.1
-
13
-
-
0031594013
-
Confidence estimation for speculation control
-
Barcelona, Spain
-
D. Grunwald, A. Klauser, S. Manne, A. Pleszkun, Confidence estimation for speculation control, in: Proceedings of the ISCA 25, Barcelona, Spain, 1998, pp. 122-131.
-
(1998)
In: Proceedings of the ISCA 25
, pp. 122-131
-
-
Grunwald, D.1
Klauser, A.2
Manne, S.3
Pleszkun, A.4
-
14
-
-
0031270791
-
Trends in semiconductor memories
-
Katayama Y. Trends in semiconductor memories. IEEE Micro. 17:1997;10-17.
-
(1997)
IEEE Micro
, vol.17
, pp. 10-17
-
-
Katayama, Y.1
-
15
-
-
0342772441
-
Challenges, not roadblocks
-
Killian E. Challenges, not roadblocks. Computer. 31:1998;44-45.
-
(1998)
Computer
, vol.31
, pp. 44-45
-
-
Killian, E.1
-
16
-
-
0031594004
-
Selective eager execution on the polypath architecture
-
Barcelona, Spain
-
A. Klauser, A. Paithankar, D. Grunwald, Selective eager execution on the polypath architecture, in: Proceedings of the ISCA 25, Barcelona, Spain, 1998, pp. 250-259.
-
(1998)
In: Proceedings of the ISCA 25
, pp. 250-259
-
-
Klauser, A.1
Paithankar, A.2
Grunwald, D.3
-
17
-
-
0032204608
-
New direction for computer architecture research
-
Kozyrakis C.E., Patterson D.A. New direction for computer architecture research. Computer. 31:1998;24-32.
-
(1998)
Computer
, vol.31
, pp. 24-32
-
-
Kozyrakis, C.E.1
Patterson, D.A.2
-
18
-
-
21744451773
-
The performance potential of value and dependence prediction
-
Lipasti M.H., Shen J.P. The performance potential of value and dependence prediction. Lect. Notes Comput. Sci. 1300:1997;1043-1052.
-
(1997)
Lect. Notes Comput. Sci.
, vol.1300
, pp. 1043-1052
-
-
Lipasti, M.H.1
Shen, J.P.2
-
19
-
-
0031233906
-
Superspeculative microarchitecture for beyond AD 2000
-
Lipasti M.H., Shen J.P. Superspeculative microarchitecture for beyond AD 2000. Computer. 30:1997;59-66.
-
(1997)
Computer
, vol.30
, pp. 59-66
-
-
Lipasti, M.H.1
Shen, J.P.2
-
20
-
-
2842554734
-
Value locality and load value prediction
-
Cambridge, MA
-
M.H. Lipasti, C.B. Wilkerson, J.P. Shen, Value locality and load value prediction, in: Proceedings of the ASPLOS VII, Cambridge, MA, 1996, pp. 138-147.
-
(1996)
In: Proceedings of the ASPLOS VII
, pp. 138-147
-
-
Lipasti, M.H.1
Wilkerson, C.B.2
Shen, J.P.3
-
21
-
-
0003506711
-
Combining branch predictors
-
Digital Western Research Laboratory
-
S. McFarling, Combining branch predictors, WRL Technical Notes TN-36, Digital Western Research Laboratory, 1993.
-
(1993)
WRL Technical Notes TN-36
-
-
McFarling, S.1
-
22
-
-
0042073882
-
Simultaneous multithreading and multimedia
-
Orlando, FL
-
H. Oehring, U. Sigmund, T. Ungerer, Simultaneous multithreading and multimedia, in: Proceedings of the Workshop on Multi-Threaded Execution, Architecture and Compilation, Orlando, FL, 1999.
-
(1999)
In: Proceedings of the Workshop on Multi-Threaded Execution, Architecture and Compilation
-
-
Oehring, H.1
Sigmund, U.2
Ungerer, T.3
-
23
-
-
84976705456
-
Improving the accuracy of dynamic branch prediction using branch correlation
-
Boston, MA
-
S.-T. Pan, K. So, J.T. Rahmeh, Improving the accuracy of dynamic branch prediction using branch correlation, in: Proceedings of the ASPLOS V, Boston, MA, 1992, pp. 76-84.
-
(1992)
In: Proceedings of the ASPLOS V
, pp. 76-84
-
-
Pan, S.-T.1
So, K.2
Rahmeh, J.T.3
-
24
-
-
0031235595
-
Billion transistors, one uniprocessor, one chip
-
Patt Y.N., Patel S.J., Evers M., Friendly D.H., Stark J. Billion transistors, one uniprocessor, one chip. Computer. 30:1997;51-57.
-
(1997)
Computer
, vol.30
, pp. 51-57
-
-
Patt, Y.N.1
Patel, S.J.2
Evers, M.3
Friendly, D.H.4
Stark, J.5
-
25
-
-
0031374420
-
Trace processors
-
Research Triangle Park, NC
-
E. Rotenberg, Q. Jacobson, Y. Sazeides, J.E. Smith, Trace processors, in: Proceedings of the MICRO-30, Research Triangle Park, NC, 1997, pp. 138-148.
-
(1997)
In: Proceedings of the MICRO-30
, pp. 138-148
-
-
Rotenberg, E.1
Jacobson, Q.2
Sazeides, Y.3
Smith, J.E.4
-
26
-
-
0013002870
-
Managing problems at high speed
-
Rubinfeld P.I. Managing problems at high speed. Computer. 31:1998;47-48.
-
(1998)
Computer
, vol.31
, pp. 47-48
-
-
Rubinfeld, P.I.1
-
27
-
-
78149276203
-
Efficiency and performance impact of value prediction
-
Paris, France
-
B. Rychlik, J. Faistl, B. Krug, J.P. Shen, Efficiency and performance impact of value prediction, in: Proceedings of the PACT, Paris, France,1998, pp. 148-154.
-
(1998)
In: Proceedings of the PACT
, pp. 148-154
-
-
Rychlik, B.1
Faistl, J.2
Krug, B.3
Shen, J.P.4
-
28
-
-
84889036959
-
Identifying bottlenecks in multithreaded superscalar multiprocessors
-
Sigmund U., Ungerer T. Identifying bottlenecks in multithreaded superscalar multiprocessors. Lect. Notes Comput. Sci. 1123:1996;797-800.
-
(1996)
Lect. Notes Comput. Sci.
, vol.1123
, pp. 797-800
-
-
Sigmund, U.1
Ungerer, T.2
-
30
-
-
0031234685
-
Trace processors: Moving to fourth-generation microarchitectures
-
Smith J.E., Vajapeyam S. Trace processors: moving to fourth-generation microarchitectures. Computer. 30:1997;68-74.
-
(1997)
Computer
, vol.30
, pp. 68-74
-
-
Smith, J.E.1
Vajapeyam, S.2
-
31
-
-
0032316241
-
Understanding the differences between value prediction and instruction reuse
-
Dallas, TX
-
A. Sodani, G.S. Sohi, Understanding the differences between value prediction and instruction reuse, in: Proceedings of the MICRO-31, Dallas, TX, 1998.
-
(1998)
In: Proceedings of the MICRO-31
-
-
Sodani, A.1
Sohi, G.S.2
-
32
-
-
0009438621
-
Multiscalar: Another fourth-generation processor
-
Sohi G.S. Multiscalar: another fourth-generation processor. Computer. 30:1997;72.
-
(1997)
Computer
, vol.30
, pp. 72
-
-
Sohi, G.S.1
-
33
-
-
0029182711
-
Multiscalar processors
-
Santa Margherita Ligure, Italy
-
G.S. Sohi, S.E. Breach, T.N. Vijaykumar, Multiscalar processors, in: Proceedings of the ISCA 22, Santa Margherita Ligure, Italy, 1995, pp. 414-425.
-
(1995)
In: Proceedings of the ISCA 22
, pp. 414-425
-
-
Sohi, G.S.1
Breach, S.E.2
Vijaykumar, T.N.3
-
34
-
-
0009598477
-
Increasing work, pushing the clock
-
Tremblay M. Increasing work, pushing the clock. Computer. 31:1998;40-41.
-
(1998)
Computer
, vol.31
, pp. 40-41
-
-
Tremblay, M.1
-
35
-
-
0029183524
-
Simultaneous multithreading: Maximizing on-chip parallelism
-
Santa Margherita Ligure, Italy
-
D.M. Tullsen, S.J. Eggers, H.M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, in: Proceedings of the ISCA 22, Santa Margherita Ligure, Italy, 1995, pp. 392-403.
-
(1995)
In: Proceedings of the ISCA 22
, pp. 392-403
-
-
Tullsen, D.M.1
Eggers, S.J.2
Levy, H.M.3
-
36
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
Philadelphia, PA
-
D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, in: Proceedings of the ISCA 23, Philadelphia, PA, 1996, pp. 191-202.
-
(1996)
In: Proceedings of the ISCA 23
, pp. 191-202
-
-
Tullsen, D.M.1
Eggers, S.J.2
Emer, J.S.3
Levy, H.M.4
Lo, J.L.5
Stamm, R.L.6
-
38
-
-
0343207128
-
A compiler technique for speculative execution of alternative program paths targeting multithreaded architectures
-
New Haven, CT
-
A. Unger, T. Ungerer, E. Zehendner, A compiler technique for speculative execution of alternative program paths targeting multithreaded architectures, in: Proceedings of the Yale Multithreaded Programming Workshop, New Haven, CT, 1998.
-
(1998)
In: Proceedings of the Yale Multithreaded Programming Workshop
-
-
Unger, A.1
Ungerer, T.2
Zehendner, E.3
-
39
-
-
0009314677
-
Static speculation, dynamic resolution
-
Linkoping, Sweden
-
A. Unger, T. Ungerer, E. Zehendner, Static speculation, dynamic resolution, in: Proceedings of the Seventh Workshop on Compilers for Parallel Computers, Linkoping, Sweden, 1998, pp. 243-253.
-
(1998)
In: Proceedings of the Seventh Workshop on Compilers for Parallel Computers
, pp. 243-253
-
-
Unger, A.1
Ungerer, T.2
Zehendner, E.3
-
40
-
-
0030644743
-
Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
-
Denver, CO
-
S. Vajapeyam, T. Mitra, Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences, in: Proceedings of the ISCA 24, Denver, CO, 1997, pp. 1-12.
-
(1997)
In: Proceedings of the ISCA 24
, pp. 1-12
-
-
Vajapeyam, S.1
Mitra, T.2
-
42
-
-
0026867221
-
Alternative implementation of two-level adaptive branch prediction
-
Gold Coast, Australia
-
T.-Y. Yeh, Y.N. Patt, Alternative implementation of two-level adaptive branch prediction, in: Proceedings of the ISCA 19, Gold Coast, Australia, 1992, pp. 124-134.
-
(1992)
In: Proceedings of the ISCA 19
, pp. 124-134
-
-
Yeh, T.-Y.1
Patt, Y.N.2
-
43
-
-
0027307813
-
A comparision of dynamic branch predictors that use two levels of branch history
-
San Diego, CA
-
T.-Y. Yeh, Y.N. Patt, A comparision of dynamic branch predictors that use two levels of branch history, in: Proceedings of the ISCA 20, San Diego, CA, 1993, pp. 257-266.
-
(1993)
In: Proceedings of the ISCA 20
, pp. 257-266
-
-
Yeh, T.-Y.1
Patt, Y.N.2
|