Analysis and optimization of structured power-ground networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 11, 2003, Pages 1533-1544

  Su, Haihua ^a   Gala, Kaushik H ^b   Sapatnekar, Sachin S ^c  

^a IBM   (United States)

^b MOTOROLA INC   (United States)

^c University of Minnesota   (United States)

Author keywords

Circuit optimization; Circuit topology; CMOS integrated circuits; Power distribution; Reduced order systems; Sensitivity

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; PARTIAL DIFFERENTIAL EQUATIONS; SENSITIVITY ANALYSIS;

CIRCUIT OPTIMIZATION; HIERARCHICAL ANALYSIS; NETWORK SIMULATOR;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0242720636     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818372     Document Type: Article

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