A high-performance ramp-voltage-scan winner-take-all circuit in an open loop architecture

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 41, Issue 4 B, 2002, Pages 2301-2305

  Ito, Kiyoto ^a   Ogawa, Makoto ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Associative memory; CMOS; Integrated circuits; Parallel computing; Vector quantization; Winner take all; WTA

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; SIGNAL PROCESSING; VECTOR QUANTIZATION;

ASSOCIATIVE MEMORY; CMOS; WINNER-TAKE-ALL; WTA;

INTEGRATED CIRCUITS;

EID: 0242507000     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.41.2301     Document Type: Article

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