The impact of tolerance on kill ratio estimation for memory

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn 2000-January, Issue , 2000, Pages 175-180

  Patterson, Oliver D ^a   Hansen, Mark H ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

Analytical models; Circuits; Data analysis; Fabrication; Inspection; Pareto analysis; Testing; Yield estimation

Indexed keywords

ANALYTICAL MODELS; DATA REDUCTION; DEFECTS; ESTIMATION; FABRICATION; INSPECTION; INSPECTION EQUIPMENT; MACHINE TOOLS; MANUFACTURE; NETWORKS (CIRCUITS); TESTING;

EFFECTIVE APPROACHES; ELECTRICAL TEST DATA; IN-LINE INSPECTIONS; INSPECTION TOOLS; MAXIMUM DISTANCE; PARAMETER SETTING; PARETO ANALYSIS; YIELD ESTIMATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 1542373433     PISSN: 10788743     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASMC.2000.902582     Document Type: Article

References (9)

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