An integrated 10 GHz quadrature LC-VCO in SiGe:C BiCMOS technology for low-jitter applications

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 293-296

  Herzel, Frank ^a   Winkler, Wolfgang ^a   Borngräber, Johannes ^a  

^a IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CARBON; INTEGRATED CIRCUIT LAYOUT; JITTER; PHASE LOCKED LOOPS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DOPING; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

BIPOLAR FREQUENCY DIVIDER; POWER CONSUMPTION; SILICON GERMANIUM;

CMOS INTEGRATED CIRCUITS;

EID: 0242414573     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. J. Savoj and B. Razavi, High-speed CMOS circuits for optical receivers, Boston: Kluwer Publishers, 2001.
2. J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and cata recovery circuit with a half-rate linear phase detector," IEEE Journal of Solid-State Circuits, vol. 36, pp. 761-767, May 2001.
3. B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998.
4. K. E. Ehwald, D. Knoll, B, Heinemann, K. Chang, J. Kirchgessner, R. Mauntel, I. S. Lim, J. Steele, P. Schley, B. Tillack, A. Wolff, K. Blum, W. Winkler, M. Pierschel, U. Jagdhold, R. Barth, T. Grabolla, H. J. Erzgräber, B. Hunger and H. J. Osten, "Modular integration of high-Performance SiGe:C HBTs in a deep submicron, epi-free CMOS process", in Proc. of the IEDM'99, Washington, Dec. 1999, pp. 561-564.
5. F. Herzel, G. Fischer, H. Gustat, and P. Weger, "An integrated CMOS PLL for low-jitter applications," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, pp. 427-429, June 2002.
6. H. M. Greenhouse, "Design of planar rectangular microelectronic inductors," IEEE Transactions on Parts, Hybrids, and Packaging, vol. PHP-10, No.2, June 1974.
7. C. P. Yue, C. Rye, J. Lau, T. H. Lee, and S. S. Wong, "Physical model for planar spiral inductors on silicon," in IEDM Tech. Dig., Dec. 1996, pp. 155-158.
8. K. O, "Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1249-1252, Aug. 1998.
9. F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, pp. 56-62, Jan. 1999.
10. M. Mansuri and C.-K. K. Yang, "Jitter optimization based on phase-locked loop design parameters," IEEE J. Solid-State Circuits, vol. 37, pp. 1375-1382, Nov. 2002.
11. D. C. Lee, "Analysis of jitter in phase-locked loops," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, pp. 704-711, Nov. 2002.
12. J. A. McNeill, "Jitter in ring oscillators," IEEE J. Solid-State Circuits, vol. 32, pp. 870-879, June 1997.