High-level area and power estimation for VLSI circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 6, 1999, Pages 697-713

  Nemani, Mahadevamurty ^a,b,c   Najm, Farid N ^a  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; ESTIMATION;

HIGH-LEVEL AREA ESTIMATION; REGISTER TRANSFER LEVEL (RTL) POWER ESTIMATION;

VLSI CIRCUITS;

EID: 0032637540     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.766722     Document Type: Article

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