On achieving complete coverage of delay faults in full scan circuits using locally available lines

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 923-931

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC DELAY LINES; FLIP FLOP CIRCUITS; LOGIC GATES;

DELAY FAULT COVERAGE; SCAN CIRCUITS; TESTABILITY ENHANCEMENT;

DESIGN FOR TESTABILITY;

EID: 0033342541     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)