Test point insertion for compact test sets

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 292-301

  Geuzebroek, M J ^a   van der Linden, J Th ^a   van de Goor, A J ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE;

AUTOMATIC TEST PATTERN GENERATORS; COMPACT TEST SETS; FAULT COVERAGE; RANDOM RESISTANT FAULTS; TEST LENGTH; TEST POINT INSERTION;

INTEGRATED CIRCUIT TESTING;

EID: 0034483641     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)