Progressive Bridge Identification

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 309-318

  Vogels, Thomas J ^a   Maly, Wojciech ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC POTENTIAL;

BRIDGE SITES;

CMOS INTEGRATED CIRCUITS;

EID: 0242303068     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. W. Maly et al., "Deformations of IC Structure in Test and Yield Learning," Proc. Of IEEE International Test Conf., 2003.
2. R. Desineni et al., "A Multi-Stage Approach to Fault Identification Using Fault Tuples," ISTFA, 2003.
3. S.D. Millman, E.J. McCluskey, J.M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries," in Proc. of IEEE International Test Conference, 1990, pp. 860-870.
4. D.B. Lavo et al., "Bridging Fault Diagnosis in the Absence of Physical Information," in Proc. of IEEE International Test Conference, 1997, pp. 887-893.
5. B. Chess, D.B. Lavo, F.J. Ferguson, "Diagnosis of Realistic Bridging Faults with Single Stuck-at Information," in Proc. of IEEE/ACM International Conf. on CAD, 1995, pp. 185-192.
6. S. Venkataraman and S.B. Drummonds, "POIROT: A Logic Fault Diagnosis Tool and Its Applications," in Proc. of IEEE International Test Conference, 2000, pp. 253-262.
7. S. Venkataraman and S.B. Drummonds, "POIROT: Applications of a Logic Fault Diagnosis Tool," in IEEE Design & Test of Computers, Jan-Feb 2001, pp. 19-30.
8. S.B. Drummonds et al., "Bridging the Gap Between Logical Diagnosis and Physical Analysis," in IEEE International Workshop on Defect Based Testing (DBT'2002), Apr. 2002.
9. S. Venkataraman and W.K. Fuchs, "A Deductive Technique for Diagnosis of Bridging Faults," in Proc. of IEEE/ACM International Conf Computer-Aided Design, 1997, pp. 562-567.
10. Y. Gong and S. Chakravarty, "Locating Bridging Faults Using Dynamically Computed Stuck-At Fault Dictionaries," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 9, Sept. 1998, pp. 876-887.
11. S. Chakravarty and Y. Gong, "An Algorithm for Diagnosing Two-Line Bridging Faults in CMOS Combinational Circuits," in Proc. of the Design Automation Conf., June 1993, pp. 520-524.
12. DDQ Measurement based Diagnosis of Bridging Faults in Combinational Circuits", Journal of Electronic Testing: Theory and Applications, Vol. 3, Dec. 1992, pp. 377-385.
13. S.D. Millman and J.M. Acken, "Special Applications of the Voting Model for Bridging Faults," in IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 263-270
14. P. Maxwell and R. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," in Proc. of International Test Conference, 1993, pp. 63-72
15. M. Abromovici, M.A. Breuer, M.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, Piscataway, NJ, 1990.
16. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran," in International Symposium on Circuits and Systems, June 1985, pp. 695-698.
17. th ACM/IEEE Conf. On Design Automation, June 2000, pp. 786-789.
18. K.N. Dwarakanath, Fault Tuples: Theory and Applications, Ph.D. Thesis, Carnegie Mellon University, 2003.
19. H.K. Lee and D.S. Ha, On the Generation of Test Patterns for Combinational Circuits, Technical Report No. 12-93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University.