Effective path selection for delay fault testing of sequential circuits

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 998-1003

  Chakraborty, Tapan J ^a   Agrawal, Vishwani D ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; OPTIMIZATION;

DELAY FAULT TESTING;

SEQUENTIAL CIRCUITS;

EID: 0031380362     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)