On-the-shelf core pattern methodology for coldfire microprocessor cores

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 1100-1107

  McLaurin, Teresa L ^a   Potter, John C ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FREQUENCIES; MICROPROCESSOR CHIPS;

COLDFIRE HARD MICROPROCESSOR CORES; MEMORY LIMITATIONS; TESTER FREQUENCY;

INTEGRATED CIRCUIT TESTING;

EID: 0034476399     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)