An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 13, Issue 9, 2003, Pages 936-943

  Wu, Bing Fei ^a   Hu, Yi Qiang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Two dimensional discrete wavelet transform; VLSI

Indexed keywords

ADDERS; CALCULATIONS; COMPUTER SIMULATION; ELECTRIC FILTERS; IMAGE COMPRESSION; LOGIC DESIGN; MULTIPLYING CIRCUITS; TWO DIMENSIONAL; WAVELET TRANSFORMS;

DISCRETE WAVELET TRANSFORM; EMBEDDED INSTRUCTION CODE; PARALLEL ARITHMETIC LOGIC UNIT; SOFTWARE PACKAGE CADENCE; TWO DIMENSIONAL INVERSE DISCRETE WAVELET TRANSFORMS;

VLSI CIRCUITS;

EID: 0142091630     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2003.816509     Document Type: Letter

References (25)

1. P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993, pp. 491-538.
2. M. Vishwanath, R. M. Owens, and M. J. Irwin, "VLSI architectures for the discrete wavelet transform," IEEE Trans. Circuits Syst. II, vol. 42, pp. 305-316, May 1995.
3. M. Ferretti and D. Rizzo, "Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction," IEEE Trans. Signal Processing, vol. 48, pp. 1365-1378, May 2000.
4. M. Vishwanath, "The recursive pyramid algorithm for the discrete wavelet transform," IEEE Trans. Signal Processing, vol. 42, pp. 673-677, Mar. 1994.
5. JPEG 2000. [Online]. Available: http://www.jpeg.org/
6. M. Antonini, M. Barlaud, P. Mathieu, and I. Daubechies, "Image coding using wavelet transform," IEEE Trans. Image Processing, vol. 1, pp. 205-220, Apr. 1992.
7. G. Knowles, "VLSI architecture for the discrete wavelet transform," Electron. Lett., vol. 26, no. 15, pp. 1184-1185, July 1990.
8. S. G. Mallat, "A theory for multiresolution signal decompositions: The wavelet representation," IEEE Trans. Pattern Anal. Machine Intell., vol. 11, pp. 674-693, July 1989.
9. T. C. Denk and K. K. Parh, "Systolic VLSI architectures for 1-D discrete wavelet transforms," in Proc. 1998 32nd Asilomar Conf. Signals, Systems and Computers, vol. 2, 1998, pp. 1220-1224.
10. W. Shunjun, W. Chao, and S. Yong, "A vlsi implementation structure for wavelet decomposition filter," in Proc. 2000 IEEE Int. Conf. Multimedia and Expo, vol. 3, 2000, pp. 1399-1402.
11. T. Acharya and P. Y. Chen, "VLSI implementation of a DWT architecture," in Proc. IEEE Int. Symp. Circuits and Systems, May 1998, pp. 272-275.
12. F. Marino, D. Guevorkian, and J. T. Astola, "Highly efficient high-speed/low-power architectures for the 1-D discrete wavelet transform," IEEE Trans. Circuits Syst. II, vol. 47, Dec. 2000.
13. C. Yu, C.-A. Hsieh, and S.-J. Chen, "Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform," in Proc. IEEE 1997 Custom Integrated Circuits Conf., 1997, pp. 237-240.
14. K. Andra, C. Chakrabarti, and T. Acharya, "A VLSI architecture for lifting-based wavelet transform," in 2000 IEEE Workshop on Signal Processing Systems, 2000, pp. 70-79.
15. J.-M. Jou, Y.-H. Shiau, and C.-C. Liu, "Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme," in Proc. 2001 IEEE Int. Symp. Circuits and Systems, vol. 2, 2001, pp. 529-532.
16. S. Masud and J. V. McCanny, "Rapid VLSI of biorthogonal wavelet transform cores," in 1999 IEEE Workshop on Signal Processing Systems, 1999, pp. 291-300.
17. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1998, pp. 291-311.
18. G. Strang and T. Nguyen, Wavelets and Filter Banks. Wellesley, MA: Wellesley-Cambridge Press, 1996, pp. 272-275.
19. B.-F. Wu and C.-Y. Su, "A fast convolution algorithm for biorthogonal wavelet image compression," J. Chinese Inst. Eng., vol. 22, no. 2, pp. 179-192, 1999.
20. M.-H. Sheu, M.-D. Shieh, and S.-W. Liu, "A VLSI architecture design with lower hardware cost and less memory for separable 2-D discrete wavelet transform," in Proc. 1998 IEEE Int. Symp. Circuits and Systems, vol. 5, 1998, pp. 457-460.
21. C.-Y. Lee and W.-S. Peng, "An Efficient Algorithm and Architecture Design for Two-Dimension Separable Discrete Wavelet Transform," Master's thesis, National Chaio Tung Univ., Hsinchu, Taiwan, 1999.
22. C.-Y. Chen, Z.-L. Yang, T.-C. Wang, and L.-G. Chen, "A programmable parallel VLSI architecture for 2-D discrete wavelet transform," J. VLSI Signal Processing Syst. Signal Image and Video Technol., vol. 28, no. 3, pp. 151-163, July 2001.
23. G. Lafruit, L. Nachtergaele, J. Borman, M. Engels, and I. Bolsen, "Optimal memory organization for scalable texture codes in MPEG-4," IEEE Trans. Circuits Syst. Video Technol., vol. 9, pp. 218-243, Apr. 1999.
24. M. Ferretti and D. Rizzo, "A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme," J. VLSI Signal Processing Syst. Signal, Image and Video Technol., vol. 28, no. 3, pp. 165-185, 2001.
25. MPEG website. [Online]. Available: http://www.mpeg.org/