Highly efficient high-speed/low-power architectures for the 1-D discrete wavelet transform

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 12, 2000, Pages 1492-1502

  Marino, Francescomaria ^a   Guevorkian, David ^b   Astola, Jaakko T ^c  

^a POLITECNICO DI BARI   (Italy)

^b NOKIA RESEARCH CENTER   (United States)

^c TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC POWER SUPPLIES TO APPARATUS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS; VOLTAGE CONTROL; WAVELET TRANSFORMS;

DISCRETE WAVELET TRANSFORMS; HIGH SPEED LOWPOWER ARCHITECTURES; RECURSIVE PYRAMID ALGORITHM;

PIPELINE PROCESSING SYSTEMS;

EID: 0034459333     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.899643     Document Type: Article

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