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Volumn 28, Issue 3, 2001, Pages 151-163
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A programmable parallel VLSI architecture for 2-D discrete wavelet transform
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Author keywords
DSP architecture; JPEG 2000; Wavelet
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Indexed keywords
ALGORITHMS;
CMOS INTEGRATED CIRCUITS;
IMAGE COMPRESSION;
PARALLEL PROCESSING SYSTEMS;
STANDARDS;
TWO DIMENSIONAL;
VLSI CIRCUITS;
WAVELET TRANSFORMS;
PROGRAMMABLE PARALLEL VLSI ARCHITECTURE;
RECURSIVE PYRAMID ALGORITHM;
TWO DIMENSIONAL WAVELET TRANSFORM;
LOGIC DESIGN;
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EID: 0034952692
PISSN: 13875485
EISSN: None
Source Type: Journal
DOI: 10.1023/A:1011180506997 Document Type: Article |
Times cited : (10)
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References (12)
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