A programmable parallel VLSI architecture for 2-D discrete wavelet transform

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 28, Issue 3, 2001, Pages 151-163

  Chen, C Y ^a   Yang, Z L ^a   Wang, T C ^a   Chen, L G ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

DSP architecture; JPEG 2000; Wavelet

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; IMAGE COMPRESSION; PARALLEL PROCESSING SYSTEMS; STANDARDS; TWO DIMENSIONAL; VLSI CIRCUITS; WAVELET TRANSFORMS;

PROGRAMMABLE PARALLEL VLSI ARCHITECTURE; RECURSIVE PYRAMID ALGORITHM; TWO DIMENSIONAL WAVELET TRANSFORM;

LOGIC DESIGN;

EID: 0034952692     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011180506997     Document Type: Article

References (12)

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9. Discrete wavelet transform: Data dependence analysis and synthesis of distributed memory and control array architectures
10. VLSI implementation of discrete wavelet transform
11. Image coding using wavelet transform