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0034822557
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Implementation of high-side high-voltage RESURF LDMOS in a sub-half-micron smart-power technology
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SOA improvement by a double RESURF LDMOS technique in a power IC technology
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V. Parthasarathy, V. Khemka, R. Zhu, and A. Bose, "SOA improvement by a double RESURF LDMOS technique in a power IC technology," in IEDM Tech. Dig., 2000, pp. 75-78.
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0034448283
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Multi-voltage device integration technique for 0.5 μm BiCMOS & DMOS process
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T. Terashima, F. Yamamoto, and K. Hatasako, "Multi-voltage device integration technique for 0.5 μm BiCMOS & DMOS process," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2000, pp. 331-334.
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Terashima, T.1
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0034449133
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2 RESURF LDMOS in a 0.35 μm CMOS process
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2 RESURF LDMOS in a 0.35 μm CMOS process," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2000, pp. 335-338.
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0034447764
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A 0.35 μm, CMOS-based smart-power technology for 7 V-50 V applications
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V. Parthasarathy, R. Zhu, M. L. Ger, V. Khemka, A. Bose, R. Baird, T. Roggenbauer, D. Collins, S. Chang, P. Hui, and M. Zunino, "A 0.35 μm, CMOS-based smart-power technology for 7 V-50 V applications," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2000, pp. 317-320.
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0034448282
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LDMOS implementation in a 0.35 μm BCD technology (BCD6)
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A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, "LDMOS implementation in a 0.35 μm BCD technology (BCD6)," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2000, pp. 323-326.
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0034826465
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0.6 μm BiCMOS based 15 and 25 V LDMOS for analog applications
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Y. Kawaguchi, K. Nakamura, K. Karouji, K. Watanabe, Y. Yamaguchi, and A. Najagawa, "0.6 μm BiCMOS based 15 and 25 V LDMOS for analog applications," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2001, pp. 169-172.
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0034447743
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A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications
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J. A. van der Pol, A. W. Ludikhuize, H. G. A. Huizing, B. van Velzen, R. J. E. Hueting, J. F. Mom, G. van Lijnschoten, G. J. J. Hessels, E. F. Houghoudt, R. van Huizen, M. J. Swanenberg, J. H. H. A. Egbers, F. van den Elshout, J. J. Koning, H. Schligtenhorst, and J. Soeteman, "A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications," in Proc. Int. Symp. Power Semicond. Dev. ICs, 2000, pp. 327-330.
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Van der Pol, J.A.1
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0036540916
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A double RESURF LDMOS with drain profile engineering for improved ESD ruggedness
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V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, A. Bose, and R. Ida, "A double RESURF LDMOS with drain profile engineering for improved ESD ruggedness," IEEE Electron Device Lett., vol. 23, pp. 212-214, Apr. 2002.
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Parthasarathy, V.1
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