Multi-voltage device integration technique for 0.5 μ m BiCMOS & DMOS process

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2000, Pages 331-334

  Terashima, T ^a   Yamamoto, F ^a   Hatasako, K ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIODES; ELECTRIC EQUIPMENT; ELECTRIC RESISTANCE; GATES (TRANSISTOR); HEAT TREATMENT; MOS DEVICES; SEMICONDUCTOR DEVICE STRUCTURES;

EPITAXIAL LAYER; FULL ISOLATION DIODE; LIGHTLY DOPED DRAIN; MULTIVOLTAGE DEVICE INTEGRATION TECHNIQUE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0034448283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. LDMOS implementation by large tilt implant in 0.6 μ m BCD5 process, flash memory compatible
2. A submicron Bi-CMOS-DMOS process for 20-30 and 50V applications
3. Optimizing 60-V integrated free-wheeling diode for automotive 0.8 μ m Bi-CMOS-DMOS technology
4. Efficiency of power devices using full Cu metallization technologies