Thermo-viscoelastic analysis of deflection in CSP electronic device packages

Journal of Electronic Packaging

Volumn 125, Issue 3, 2003, Pages 414-419

  Koguchi, Hideo ^a   Sasaki, Chie ^b   Nishida, Kazuto ^b  

^a NAGAOKA UNIVERSITY OF TECHNOLOGY   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELASTIC MODULI; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTEGRATED CIRCUITS; LASER BEAMS; POISSON RATIO; STRAIN; SUBSTRATES; THERMAL EFFECTS; THERMAL EXPANSION; THERMOELASTICITY; VISCOELASTICITY;

CHIP-SCALE PACKAGE; MULTILAYERED PLATE THEORY; THERMO-VISCOELASTIC ANALYSIS;

ELECTRONICS PACKAGING;

EID: 0141918641     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.1602705     Document Type: Article

References (25)

1. Iwatsu, S., and Honda, N., 2001, "Reliability Analysis for Underfill-Encapsulated Flip Chip Packages (Direct Attach Aurum Bump Type)," JIEP Journal of Japan Institute Electronics Packaging, 4, pp. 515-518.
2. Saito, K., Hayashi, S., Takahashi, H., and Yamagata, M., 2000, "Flow Analysis of Non Conductive Resin Paste for Flip Chip Interconnection Process," Proceedings of 2000 International Symposium on Microelectronics, pp. 343-346.
3. Tamaki, K., Saza, Y., Dotta, Y., and Rai, A., 1999, "Development of Stacked CSP using Flip-Chip Technologies," Proceedings of the 1999 International Symposium on Microelectronics, pp. 33-36.
4. Nakamura, S., Kido, M., Kushizki, Y., Murakami, G., and Mita, M., 2000, "Thermo-viscoelastic Numerical Analysis of Residual Stress in a Semiconductor Device against its Material Properties," Proceedings of 2000 International Symposium on Microelectronics, pp. 331-334.
5. Nishida, K., Nishikawa, H., and Ohtani, H., 1999, "Flip-Chip Bonding Technology using a Resin Encapsulation Sheet," Proceedings of the 6th Symposium on Microjoining and Assembly Technology in Electronics (MATE '99), pp. 189-192.
6. Timoshenko, S.P., 1925, "Analysis of Bi-Metal Thermostats," J. Opt. Soc. Am., 11, pp. 233-255.
7. Lang, G. A., Feder, B. J., and Williams, W. D., 1970, "Thermal Fatigue in Silicon Power Transistor." IEEE Trans. Electron. Devices 17, pp. 787-793.
8. Chen, W.-T., and Nelson, C.W., 1979, "Thermal Stresses in Bonded Joints," IBM J. Res. Dev., 23, pp. 179-188.
9. Gui, X., Wu, W.-C., and Gao, G.-B., 1986, "An Improved Model of Thermal Stresses in Power Transistors," ACTA Electronic Sinica, 14, pp. 123-125.
10. Suhir, E., 1986, "Stresses in Bi-Metal Thermostats," ASME J. Appl. Mech., 53, pp. 657-660.
11. Suhir, E., 1986, "Calculated Thermally Induced Stresses in Adhesively Bonded and Soldered Assemblies," Proceedings of the International Symposium on Aicroelectronics, pp. 383-392.
12. Suhir, E., 1986, "Stresses in Adhesively Bobded Bi-Material Assemblies Used in Electronic Packaging," Mater. Res. Soc. Symp. Proc. No. 72 (Materials Research Society, Pittsburgh), pp. 133-138.
13. Suhir, E., 1992, "Predicted Residual Bow of Thin Plastic Packages of Integrated Circuit Devices," ASME J. Electron. Packag., 114, pp. 467-470.
14. Daniel, I.M., Wang, T.-M., and Gotro, J.T., 1990, "Thermomechanical Behavior of Multilayer Structures in Microelectronics," ASME J. Electron. Packag., 112, pp. 11-15.
15. Pan, T.-Yu., and Pao, Yi-H., 1990, "Deformation in Multilayers Stacked Assemblies," ASME J. Electron. Packag., 112, pp. 30-34.
16. Variyam, M.N., Xie, W., and Sitaraman, S.K., 2000, "Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling," ASME J. Electron. Packag., 122, pp. 121-127.
17. Hangai, Y., 1995, Basic Theory of Plate, pp. 9, Shoukokusha, Tokyo.
18. Kunio, T., 1983, Basics of Solid Mechanics, pp. 249, Baifukan, Tokyo.
19. Nakamura, S., Murakami, G., Isaka, K., Ueno, K., and Nakamura, K., 1999, "Estimation by Thermo-Viscoelastic Analysis for Warp Deformation of Flip Chip Attached LSI," JIEP Journal of Japan Institute Electronics Packaging, 2, pp. 291-297.
20. Findley, W.N., Lai, J.S., and Onaran, K., 1976, Creep and Relaxation of Nonlinear Viscoelastic Materials, pp. 100, North-Holland, Amsterdam.
21. Dang, Anh X.H., Ume, I.C., and Bhattacharya, S.K., 2000, "Measurement of Dynamic Warpage During Thermal Cycling of Dielectric Coated Ss Substrates for Large Area MCM-D Packaging," ASME J. Electron. Packag., 122, pp. 77-85.
22. Dang, Anh X.H., Ume, I.C., and Bhattacharya, S.K., 2000, "A Study on Warpage of Flexible SS Substrates for Large Area MCM-D Packaging," ASME J. Electron. Packag., 122, pp. 86-91.
23. Yao, Q., and Qu, J., 1999, "Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-Chip Packages," ASME J. Electron. Packag., 121, pp. 196-201.
24. Darbha, K., Okura, J.H., Shetty, S., Dasgupta, A., Reinikainen, T., Zhu, J., and Caers, J.F.J.M., 1999, "Thermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 2 - With Underfill," ASME J. Electron. Packag., 121, pp. 237-241.
25. Wolfram, S., 2000, The Mathematica Book, Fourth Edition, pp. 102-104, Wolfram Research, Inc., Tokyo.