Improved outline phase shifting mask(OL-PSM) for reduction of the mask error enhancement factor

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5040 II, Issue , 2003, Pages 1220-1230

  Misaka, Akio ^a   Matsuo, Takahiro ^a   Sasago, Masaru ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

ArF lithography; Centerline phase shifting mask; Mask error enhancement factor; Outline phase shifting mask; Phase shifting mask; Resolution enhancement technology

Indexed keywords

ALGORITHMS; CHROMIUM; COMPUTER SIMULATION; ELECTRIC CONTACTS; ETCHING; MASKS; PHASE SHIFTERS; PHOTORESISTS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE;

ARGON FLUORIDE LITHOGRAPHY; MASK ERROR ENHANCEMENT; PHASE SHIFTING MASK; RESOLUTION ENHANCEMENT TECHNOLOGY;

LITHOGRAPHY;

EID: 0141833147     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485319     Document Type: Conference Paper

References (6)

1. M. D. Levenson, N. S. Visnawathan and R. A. Simpson, "Improving resolution in photolithography with a phase-shifting mask", IEEE Trans. Electron Devices, 29, pp. 1828-1836, 1982.
2. T. Matsuo, T. Ogawa and H. Morimoto, "Feasibility study of an embedded transparent phase-shifting mask in ArF lithography", Proc. SPIE, 4000, pp. 443-451, 2000.
3. J. F. Chen, J. S. Petersen, R. Socha, T. Laidig, K. E. Wampler, K. Nakagawa, G. Hughes, S. MacDonald and W. Ng, "Binary halftone chromless PSM technology for λ/4 optical lithography", Proc. SPIE, 4346, pp. 515-533, 2001.
4. Hua-Yu Liu, L. Karklin, Yao-Ting Wang and Y. C. Pati, "The application of alternating phase-shifting masks to 140nm gate patterning (II)", Proc. SPIE, 3334, pp. 2-14, 1998.
5. P. Graeupner, A. Goehnermeier, M. Lowisch, R. Garreis, D. Flagello, S. Hansen, R. Socha, C. Koehler "Solutions for printing sub-100-nm contacts with ArF", Proc. SPIE, 4691, pp. 503-514, 2002.
6. A. Misaka, T. Matsuo and M. Sasago, "Super-resolution enhancement method with phase-shifting mask available for random patterns", Tech. Dig. VLSI Sympo., 200-201, 2002.