A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

IEEE Electron Device Letters

Volumn 24, Issue 9, 2003, Pages 547-549

  Pan, James ^a   Woo, Christy ^a   Ngo, Minh Van ^a   Besser, Paul ^a   Pellerin, John ^a   Xiang, Qi ^a   Lin, Ming Ren ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

Carbon; Doping; Metal; MOSFET; Phosphorus; Tantalum

Indexed keywords

CARBON; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRODES; GATES (TRANSISTOR); LOW TEMPERATURE OPERATIONS; POLYSILICON; RAPID THERMAL ANNEALING; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; TANTALUM; THERMOOXIDATION;

GATE PATTERNING; LOW TEMPERATURE METAL DOPING TECHNIQUE; METAL GATE ELECTRODE;

MOSFET DEVICES;

EID: 0141674998     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.815937     Document Type: Letter

References (8)

1. H. Shimada, I. Ohshima, S.-I.Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, and T. Ohmi, "Low resistivity bcc-Ta/TaNx metal gate MNSFET's having plane gate structure featuring fully low-temperature processing below 450°C," in VLSI Tech. Dig., 2001, pp. 67-68.
2. T. Yamada, M. Moriwaki, Y. Harada, S. Fujii, and K. Eriguchi, "The metal gate MOS reliability with the improved sputtering process for gate electrode," in IEDM Tech. Dig., 1999, pp. 319-322.
3. 2 gate dielectrics," in VLSI Tech. Dig., 2002, pp. 24-25.
4. A. Chatterjee, R. Chapman, G. Dixit, J. Kuehne, S. Hattangady, H. Yang, G. Brown, R. Aggarwal, U. Erdogan, Q. He, M. Hanratty, D. Rogers, S. Murtaza, S. Fang, R. Kraft, A. Rotondaro, J. Hu, M. Terry, W. Lee, C. Fernado, A. Konecni, G. Wells, D. Frystak, C. Brown, M. Rodder, and I. Chen, "Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process," in IEDM Tech. Dig., 1997, pp. 821-824.
5. S. Matsuda, H. Yamakawa, A. Azuma, and Y. Toyoshima, "Performance improvement of metal gate CMOS technologies," in VLSI Tech. Dig., 2001, pp. 63-64.
6. A. Yagishita, T. Saito, K. Nakjima, S. Inumiya, T. Shibata, Y. Tsunashima, K. Suguro, and T. Arikado, "Improvement of threshold voltage deviation in damascene metal gate transistors," IEEE Trans. Electron Devices vol. 48, pp. 1604-1611, Aug. 2001.
7. J. Pan, C. Woo, Q. Xiang, and M. Lin, "Measuring the work functions of PVD TaN, TaSiN and TiSiN with a Schottky Diode CV Technique for metal gate CMOS applications," in Proc. Mater. Res. Soc. Symp., vol. 745, pp. 55-60.
8. J. Pan, M. V. Ngo, C. Woo, P. Besser, B. Yu, Q. Xiang, and M.-R. Lin, "Metal gate NMOSFET's with TaSiN/TaN stacked electrode fabricated by a replacement (damascene) technique," in Proc. Int. Symp. VLSI Technol., Syst., and Applicat., Hsinchu, Taiwan, R.O.C., 2003.