Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+Buses

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Volumn , Issue , 2002, Pages 92-97

  Chen, Jun ^a   He, Lei ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Interconnect Design

Indexed keywords

ALGORITHMS; BUSES; CROSSTALK; ELECTRIC POWER SYSTEM INTERCONNECTION; SPURIOUS SIGNAL NOISE; VIRTUAL REALITY;

SUPERPOSITION ALGORITHMS;

SWITCHING CIRCUITS;

EID: 0141538177     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/589427.589430     Document Type: Conference Paper

References (12)

1. L. H. Chen and M. Marek-Sadowska, "Aggressor alignment for worst-case crosstalk noise," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 612 - 621, May 2001.
2. L. He and K. M. Lepak, "Simultaneous shielding insertion and net ordering for capacitive and inductive coupling minimization," in Proc. Int. Symp. on Physical Design, 2000.
3. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: a Systems Perspective. Addison-Wesley, second ed., 1993.
4. http://www-device.EECS.Berkeley.EDU/ptm/.
5. J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542-548, 1984.
6. F. Dartu, N. Menezes, J. Qian, and L. T. Pillage, "A gate-delay model for high-speed CMOS circuits," in Proc. Design Automation Conf, pp. 576-580, 1994.
7. P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of worst-case aggressor alignment for delay calculation," in Proc. Int. Conf. on Computer Aided Design, 1998.
8. M. Xu and L. He, "An efficient model for frequency-dependent on-chip inductance," in Great Lakes Symposium on VLSI, 2001.
9. T. Lin and L. Pileggi, "On the efficacy of simplified 2d on-chip inductance models," in Proc. Design Automation Conf, 2002.
10. L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An efficient inductance modeling for on-chip interconnects," in Proc. IEEE Custom Integrated Circuits Conference, pp. 457-460, May 1999.
11. M. W. Beattie and L. Pileggi, "IC analyses including extracted inductance model," in Proc. Design Automation Conf, 1999.
12. Y. Cao, C. M. Hu, X. Huang, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester, "Effects of global interconnect optimizations on performance estimation of deep submicron design," in Proc. Int. Conf. on Computer Aided Design, 2000.