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Volumn , Issue , 2000, Pages 86-91

Area and search space control for technology mapping

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; DATA STRUCTURES; GRAPH THEORY; HEURISTIC METHODS; OPTIMIZATION; PARETO PRINCIPLE; SET THEORY;

EID: 0033685282     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855283     Document Type: Article
Times cited : (5)

References (12)
  • 1
    • 85177129111 scopus 로고
    • Computational complexity of logic synthesis and optimization
    • K. Keutzer D. Richards Computational complexity of logic synthesis and optimization Proceedings of International Workshop on Logic Synthesis Proceedings of International Workshop on Logic Synthesis 1989-May
    • (1989)
    • Keutzer, K.1    Richards, D.2
  • 2
    • 0001950218 scopus 로고
    • Technology binding and local optimization by dag mapping
    • K. Keutzer Technology binding and local optimization by dag mapping Proceedings of the 24th ACM/IEEE Design Automation Conference 341 347 Proceedings of the 24th ACM/IEEE Design Automation Conference 1987-June
    • (1987) , pp. 341-347
    • Keutzer, K.1
  • 7
    • 0008527351 scopus 로고    scopus 로고
    • Delay-optimal technology mapping by dag covering
    • Y. Kukimoto R. K. Brayton P. Sawkar Delay-optimal technology mapping by dag covering DAC DAC 1998-June
    • (1998)
    • Kukimoto, Y.1    Brayton, R.K.2    Sawkar, P.3
  • 8
    • 85177104618 scopus 로고
    • A nearly optimal algorithm for Technology Mapping minimizing Area under Delay Constraints
    • K. Chaudhary M. Pedram A nearly optimal algorithm for Technology Mapping minimizing Area under Delay Constraints Proceedings of 29th Design Automation Conference 491 498 Proceedings of 29th Design Automation Conference 1992-June
    • (1992) , pp. 491-498
    • Chaudhary, K.1    Pedram, M.2
  • 9
    • 0003275249 scopus 로고
    • Advanced Research in VLSI
    • The theory of logical effort: designing for speed on the back of an envelope UC Santa Cruz
    • I. Sutherland R. Sproull Advanced Research in VLSI 1991 UC Santa Cruz The theory of logical effort: designing for speed on the back of an envelope
    • (1991)
    • Sutherland, I.1    Sproull, R.2
  • 10
    • 85177139394 scopus 로고    scopus 로고
    • Wavefront technology mapping
    • M. Iyer L. Stok A. Sullivan Wavefront technology mapping International Workshop on Logic Synthesis International Workshop on Logic Synthesis 1998
    • (1998)
    • Iyer, M.1    Stok, L.2    Sullivan, A.3
  • 11
    • 0003642415 scopus 로고
    • Performance-oriented technology mapping
    • H. J. Touati C. W. Moon R. K. Brayton A. Wang Performance-oriented technology mapping Proceedings of the 6th MIT conference:Advanced Research in VLSI 79 97 Proceedings of the 6th MIT conference:Advanced Research in VLSI 1990
    • (1990) , pp. 79-97
    • Touati, H.J.1    Moon, C.W.2    Brayton, R.K.3    Wang, A.4
  • 12
    • 85177108643 scopus 로고    scopus 로고
    • Planning for performance
    • R.H.J.M. Otten R. K. Brayton Planning for performance DAC DAC 1998-June
    • (1998)
    • Otten, R.H.J.M.1    Brayton, R.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.