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Volumn 2002-January, Issue , 2002, Pages 112-119

Testing of analogue circuits via (standard) digital gates

Author keywords

Aerospace testing; Automotive engineering; Circuit testing; Costs; Design for testability; Digital integrated circuits; Logic gates; Proposals; Software libraries; Voltage

Indexed keywords

ANALOG CIRCUITS; AUTOMOTIVE ENGINEERING; CAPACITANCE; COST ENGINEERING; COSTS; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT TESTING; LOGIC GATES; SOFTWARE TESTING;

EID: 0041745614     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996709     Document Type: Conference Paper
Times cited : (28)

References (10)
  • 1
    • 0031175881 scopus 로고    scopus 로고
    • On-line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits
    • C. Metra, M. Favalli, P. Olivo, B. Riccò "On-line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits}, IEEE Trans. on Computer Aided Design, vol. 16, 1997, p.770-775.
    • (1997) IEEE Trans. on Computer Aided Design , vol.16 , pp. 770-775
    • Metra, C.1    Favalli, M.2    Olivo, P.3    Riccò, B.4
  • 2
    • 0030398941 scopus 로고    scopus 로고
    • Early Capture for Boundary Scan Timing Measurements
    • K. Loftstrom, "Early Capture for Boundary Scan Timing Measurements", proc. ITC, 1996, pp. 417-422.
    • (1996) Proc. ITC , pp. 417-422
    • Loftstrom, K.1
  • 3
    • 0031380352 scopus 로고    scopus 로고
    • A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signals
    • R. D. Adams, E. S. Cooley, P. R. Hansen, "A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signals", proc. ITC, 1997, pp. 217-225.
    • (1997) Proc. ITC , pp. 217-225
    • Adams, R.D.1    Cooley, E.S.2    Hansen, P.R.3
  • 4
    • 0008761975 scopus 로고    scopus 로고
    • Bias-Programmable Hardware Reconfiguration for On-Chip Test Response Evaluation
    • June 21-23, Montpellier, France
    • D. De Venuto, M. J. Ohletz, "Bias-Programmable Hardware Reconfiguration for On-Chip Test Response Evaluation", IEEE proc. IMSTW 2000, June 21-23, Montpellier, France, 2000, pp. 58-63.
    • (2000) IEEE Proc. IMSTW 2000 , pp. 58-63
    • De Venuto, D.1    Ohletz, M.J.2
  • 5
    • 27844563866 scopus 로고    scopus 로고
    • On-Chip Signal Level Evaluation for Mixed-Signal ICs using Digital Window Comparators
    • 29 May - 1 June Stockholm, Sweden, 2001
    • D. De Venuto, M. J. Ohletz, B. Riccò, "On-Chip Signal Level Evaluation for Mixed-Signal ICs using Digital Window Comparators", Proc. IEEE ETW01, 29 May - 1 June 2001, Stockholm, Sweden, 2001 pp. 175-179.
    • (2001) Proc. IEEE ETW01 , pp. 175-179
    • De Venuto, D.1    Ohletz, M.J.2    Riccò, B.3
  • 6
    • 0035373236 scopus 로고    scopus 로고
    • On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Refernce Voltages
    • Kluwer Academic Publishers, The Netherlands, June
    • D. De Venuto, M. J. Ohletz, "On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Refernce Voltages", Journal of Electronic Testing, 17, Kluwer Academic Publishers, The Netherlands, June 2001, pp. 243-253.
    • (2001) Journal of Electronic Testing , vol.17 , pp. 243-253
    • De Venuto, D.1    Ohletz, M.J.2
  • 9
    • 0030409505 scopus 로고    scopus 로고
    • Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits
    • M. J. Ohletz, "Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits", proc. ITC, 1996, pp.776-785.
    • (1996) Proc. ITC , pp. 776-785
    • Ohletz, M.J.1
  • 10
    • 0018495077 scopus 로고
    • Fault Dictionary based upon Stimulus Design
    • July
    • H.H. Schreiber: "Fault Dictionary based upon Stimulus Design", Trans. Circuits and Systems, Vol. 26, No. 7, July 1979, pp. 529-537.
    • (1979) Trans. Circuits and Systems , vol.26 , Issue.7 , pp. 529-537
    • Schreiber, H.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.