메뉴 건너뛰기




Volumn 2001, Issue , 2001, Pages 68-72

On-chip signal level evaluation for mixed-signal ICs using digital window comparators

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATORS (OPTICAL); DIGITAL LIBRARIES;

EID: 27844563866     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2001.946664     Document Type: Conference Paper
Times cited : (5)

References (8)
  • 1
    • 0031175881 scopus 로고    scopus 로고
    • On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
    • C. Mara, M. Favalli, P. Olivo, B. Riccô "On-line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits", IEEE Trans, on Computer Aided Design, Vol. 16, p.770, 1997.
    • (1997) IEEE Trans, on Computer Aided Design , vol.16 , pp. 770
    • Mara, C.1    Favalli, M.2    Olivo, P.3    Riccô, B.4
  • 2
    • 0030398941 scopus 로고    scopus 로고
    • Early capture for boundary scan timing measurements
    • K. Loftstrom, "Early Capture for Boundary Scan Timing Measurements", Proc. ITC, pp. 417-22, 1996
    • (1996) Proc. ITC , pp. 417-422
    • Loftstrom, K.1
  • 3
    • 0031380352 scopus 로고    scopus 로고
    • A self-test circuit for evaluating memory sense-amplifier signals
    • R. D. Adams, E. S. Cooley, P. R. Hansen, "A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signals", Proc. ITC, pp. 217-225, 1997
    • (1997) Proc. ITC , pp. 217-225
    • Adams, R.D.1    Cooley, E.S.2    Hansen, P.R.3
  • 4
    • 0008761975 scopus 로고    scopus 로고
    • Bias-programmable hardware reconfiguration for on-chip test response evaluation
    • June 21-23 Montpellier, France
    • D. De Venuto, M. J. Ohletz, "Bias-Programmable Hardware Reconfiguration for On-Chip Test Response Evaluation", IEEE proc. IMSTW 2000, June 21-23, 2000 Montpellier, France.
    • (2000) IEEE Proc. IMSTW 2000
    • De Venuto, D.1    Ohletz, M.J.2
  • 5
    • 85037581705 scopus 로고    scopus 로고
    • Static and dynamic on-chip test response evaluation using a two-mode comparator
    • May 23-26 Cascais, Portugal
    • D. De Venuto, M. J. Ohletz, G. Matarrese, "Static and Dynamic On-Chip Test Response Evaluation using a Two-Mode Comparator", ETW 2000, May 23-26, pp. 47-52 Cascais, Portugal.
    • ETW 2000 , pp. 47-52
    • De Venuto, D.1    Ohletz, M.J.2    Matarrese, G.3
  • 7
    • 0030409505 scopus 로고    scopus 로고
    • Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits
    • M. J. Ohletz, "Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits", proc. ITC, pp. 776-785, 1996
    • (1996) Proc. ITC , pp. 776-785
    • Ohletz, M.J.1
  • 8
    • 0018495077 scopus 로고
    • Fault dictionary based upon stimulus design
    • July
    • H.H. Schreiber: "Fault Dictionary based upon Stimulus Design", Trans. Circuits and Systems, Vol. 26, No. 7, July 1979.
    • (1979) Trans. Circuits and Systems , vol.26 , Issue.7
    • Schreiber, H.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.