On-chip test for mixed-signal ASICs using two-mode comparators with bias-programmable reference voltages

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 3-4, 2001, Pages 243-253

  De Venuto, Daniela ^a   Ohletz, Michael J ^b  

^a POLITECNICO DI BARI   (Italy)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

Bias programming; DfT; GO NOGO test; Hardware conversion; Mixed signal ASIC; Overhead; Power consumption

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ESTIMATION; HYSTERESIS; MATHEMATICAL PROGRAMMING; OPERATIONAL AMPLIFIERS;

ANALOGUE FUNCTIONAL BLOCKS; AUTOMATED TEST EQUIPMENT; BIAS-PROGRAMMABLE REFERENCE VOLTAGE; ON-CHIP TEST; TWO-MODE COMPARATOR;

DESIGN FOR TESTABILITY;

EID: 0035373236     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1013377811693     Document Type: Article

References (13)

1. Early capture for boundary scan timing measurements
2. A self-test circuit for evaluating memory sence-amplifier signals
3. Built-in self-test proposal for mixed-signal circuits
4. Built-in logic block observation techniques
5. VLSI Testing
6. Bias-programmable hardware reconfiguration for on-chip test response evaluation
7. Static and dynamic on-chip test response evaluation using a two-mode comparator
8. Fault dictionary based upon stimulus design
9. Realistic faults of mapping scheme for the fault simulation of integrated analogue CMOS circuits