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Volumn , Issue , 2003, Pages 974-977

Architectural selection of A/D converters

Author keywords

A D conversion; Power estimation

Indexed keywords

COMPUTER AIDED DESIGN; ESTIMATION; MODULATORS; POWER ELECTRONICS; VLSI CIRCUITS;

EID: 0041633548     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776072.776076     Document Type: Conference Paper
Times cited : (19)

References (10)
  • 1
    • 0002379498 scopus 로고
    • Oversampling methods for A/D and D/A conversion
    • IEEE Press
    • J. Candy and G. C. Temes. Oversampling methods for A/D and D/A conversion. In Oversampling ΔΣ converters, pages 1-25. IEEE Press, 1992.
    • (1992) Oversampling ΔΣ Converters , pp. 1-25
    • Candy, J.1    Temes, G.C.2
  • 4
    • 0033358697 scopus 로고    scopus 로고
    • A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwith of 1.1 MHz for ADSL applications
    • Y. Geerts, A. Marques, M. Steyaert, and W. Sansen. A 3.3-V, 15-bit, Delta-Sigma ADC with a signal bandwith of 1.1 MHz for ADSL applications. IEEE Journal Solid-State Circuits, 34(7):927-936, 1999.
    • (1999) IEEE Journal Solid-State Circuits , vol.34 , Issue.7 , pp. 927-936
    • Geerts, Y.1    Marques, A.2    Steyaert, M.3    Sansen, W.4
  • 5
    • 0032259908 scopus 로고    scopus 로고
    • Systematic design for optimization of high-speed self-calibrated pipelined a/d converters
    • december
    • J. Goes, J. C. Vital, and J. E. Franca. Systematic design for optimization of high-speed self-calibrated pipelined a/d converters. IEEE Trans. Circuits and Systems II, 45:1513-1526, december 1998.
    • (1998) IEEE Trans. Circuits and Systems II , vol.45 , pp. 1513-1526
    • Goes, J.1    Vital, J.C.2    Franca, J.E.3
  • 6
    • 0029701860 scopus 로고    scopus 로고
    • Impact of transistor mismatch on the speed-accuracy-power tradeoff of analog cmos circuits
    • May
    • P. Kinget and M. Steyaert. Impact of transistor mismatch on the speed-accuracy-power tradeoff of analog cmos circuits. In Proc. Custom Integrated Circuits Conference, pages 333-336, May 1996.
    • (1996) Proc. Custom Integrated Circuits Conference , pp. 333-336
    • Kinget, P.1    Steyaert, M.2
  • 7
    • 0002528332 scopus 로고    scopus 로고
    • A power estimation model for high-speed CMOS A/D converters
    • IEEE
    • E. Lauwers and G. Gielen. A power estimation model for high-speed CMOS A/D converters. In Proceedings of DATE, pages 401-405. IEEE, 1999.
    • (1999) Proceedings of DATE , pp. 401-405
    • Lauwers, E.1    Gielen, G.2
  • 9
    • 0031169153 scopus 로고    scopus 로고
    • A 1.8V digital-audio sigma-delta modulator in 0.8-μm CMOS
    • June
    • S. Rabii and B. A. Wooley. A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8-μm CMOS. IEEE Journal of Solid-State Circuits, 32:783-796, June 1997.
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , pp. 783-796
    • Rabii, S.1    Wooley, B.A.2
  • 10
    • 0036544662 scopus 로고    scopus 로고
    • Speed-power-accuracy tradeoff in high-speed cmos adcs
    • april
    • K. Uyttenhove and M. S. J. Steyaert. Speed-power-accuracy tradeoff in high-speed cmos adcs. IEEE Trans. On Circ. and Syst., 49:280-287, april 2002.
    • (2002) IEEE Trans. On Circ. and Syst. , vol.49 , pp. 280-287
    • Uyttenhove, K.1    Steyaert, M.S.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.