Virtual compression through test vector stitching for scan based designs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 104-109

  Rao, Wenjing ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCIAL IMPLEMENTATION; COMPRESSION TECHNIQUES; FAULT COVERAGES; SCAN-BASED DESIGNS; SOC TESTING; TEST APPLICATION TIME; TEST VECTORS; TESTER MEMORY;

DESIGN; EXHIBITIONS;

VECTORS;

EID: 0041479139     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253594     Document Type: Conference Paper

References (8)

1. A. Jas, B. Pouya and N. A. Touba, ?Virtual Scan Chains: A Means for Reducing Scan Length in Cores?, in ITC, pp. 73-78, 2000
2. A. Jas, K. Mohanram and N. A. Touba, ?An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets?, in ATS, pp. 275-280, 1999
3. I. Hamzaoglu and J. Patel, ?Reducing Test Application Time for Full Scan Embedded Cores?, in FTCS, pp. 260-267, 1999
4. I. Bayraktaroglu and A. Orailoglu, ?Test Volume and Application Time Reduction Through Scan Chain Concealment?, in DAC, pp. 151-155, 2001
5. S. Reda and A. Orailoglu, ?Reducing Test Application Time Through Test Data Mutation Encoding?, in DATE, pp. 387-393, 2002
6. C. Su and K. Hwang, ?A Serial Scan Test Vector Compression Methodology?, in ITC, pp. 981-988, 1993
7. H. K. Lee and D. S. Ha, ?On the Generation of Test Patterns for combinational Circuits?, Technical report 12-93, Dep?t of Electrical Eng., Virginia Polytechnic Institute and State University, 1993
8. H. K. Lee and D. S. Ha, ?HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits?, in DAC, pp. 336-340, 1992