High-level synthesis for low power based on network flow method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 3, 2003, Pages 364-375

  Lyuh, Chun Gi ^a   Kim, Taewhan ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

High level synthesis; Low power architecture design; Module binding

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SCHEDULING;

HIGH LEVEL SYNTHESIS; LOW POWER ARCHITECTURE DESIGN; MAX FLOW COMPUTATION; MODULE BINDING; NETWORK FLOW METHOD;

COMPUTER NETWORKS;

EID: 0041418155     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.810796     Document Type: Article

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