Integrated inductors modeling for library development and layout generation

Analog Integrated Circuits and Signal Processing

Volumn 35, Issue 2-3, 2003, Pages 121-132

  Sendra, José R ^a   Del Pino, Javier ^a   Hernández, Antonio ^a   González, Benito ^a   García, Javier ^a   García Alonso, Andrés ^b   Nunez, Antonio ^a  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b CEIT   (Spain)

Author keywords

CAD tools; Integrated inductor; RFIC

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL LIBRARIES; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON;

CONVENTIONAL LUMPED EQUIVALENT CIRCUIT; INTEGRATED INDUCTORS;

ELECTRIC INDUCTORS;

EID: 0041347960     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024122430963     Document Type: Article

References (12)

1. Del Pino, J., Sendra, J. R., Hernández, A.; Khemchandani, S. L., Aguilera, J., González, B., García, J. and Nunez, A., "Models and tools for CMOS integrated inductors." Int. Journal of Analog Integrated Circuits and Signal Processing, accepted for publication, 2002.
2. Larson, L. E., Case, M., Rosenbaum, S. and Rensh, D., "Si/SiGe HBT technology for low cost monolithic microwave integrated circuits," in Proc. 1996 International Solid State Circuits Conference, pp. 80-81, 1996.
3. Ozgur, M., Zaghloul, M. E. and Gaitan, M., "High Q backside micromachined CMOS inductors," in Proc. 1999 IEEE International Symposium on Circuits and Systems 2, pp. 577-580, 1999.
4. Ashby, K. B., Koullias, I. A., Finley, W. C., Bastek, J. J. and Moinian, S., "High Q inductors for wireless applications in a complementary silicon bipolar process." IEEE Journal of Solid-State Circuits 31(1), pp. 4-9, 1996.
5. Niknejad, A. M., Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates. Ph.D. Dissertation. University of California at Berkeley, April 2000.
6. Craninckx, J. and Steyaert, M. S. J., "A 1.8 GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors." IEEE Journal of Solid-State Circuits 32(5), pp. 736-744, May 1997.
7. Yue, C. P., Ryu, C., Lau, J., Lee, T. H. and Wong, S. S., "A physical model for planar spiral inductors on silicon." Int. Electron Dev. Meeting Dig. Tech. Papers, pp. 155-158, December 1996.
8. Lee, T. H., The Design of CMOS RF Integrated Circuits. Cambridge University Press, 1998.
9. www.cadence.com
10. Waldow, P. and Wolff, I., "Dual bounds variational formulation of skin effect problems." IEEE MTT-S Int. Microwave Symp. Dig., pp. 333-336, 1987.
11. Javier del Pino, "Physically based improvement of integrated inductor model." Internal Report, 2001.
12. Power, J. A., Kelly, S. C., Griffith, E. C. and O'Neill, M., "An investigation of on-chip spiral inductors on a 0.6 μm BiCMOS technology for RF applications," in Proc. IEEE 1999 Int. Conf. on Microelectronics Test Structures 12, pp. 18-23, March 1999.