Noise margin constraints for interconnectivity in deep submicron low power and mixed-signal VLSI circuits

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 123-136

  Zheng, Li Rong ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRIC WIRING; GEOMETRY; INTEGRATED CIRCUIT MANUFACTURE; LOW POWER ELECTRONICS; MIXED SIGNAL INTEGRATED CIRCUITS; TIMING CIRCUITS; VLSI CIRCUITS;

CROSS-SECTION AREA; DEEP SUBMICRON CMOS; DIFFERENT GEOMETRY; GLOBAL INTERCONNECTS; INTERCONNECT DENSITIES; INTERCONNECT LAYERS; LOCAL INTERCONNECTS; PROCESS TECHNOLOGIES;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0008363830     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756043     Document Type: Conference Paper

References (12)

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