Reliability test guidelines for a 0.18 μm generation multi-oxide CMOS technology for system-on-chip applications

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 1928-1932

  Chen, Shang Jr ^a   Lin, Ching Chung ^a   Chung, Steve Shao Shiun ^a   Lin, Jung Chun ^a   Chu, Chih Hsiun ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Device lifetime; Multi oxide technology; Negative bias temperature instability; Reliability issue; System on a chip; Temperature effect

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); HOT CARRIERS; RELIABILITY; SEMICONDUCTOR DEVICE TESTING; THERMAL EFFECTS; THERMAL STRESS;

MULTI-OXIDE TECHNOLOGY; NEGATIVE BIAS TEMPERATURE INSTABILITY; SYSTEM-ON-A-CHIP;

MOSFET DEVICES;

EID: 0038686571     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.42.1928     Document Type: Article

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