A coarse-grained FPGA architecture for reconfigurable baseband modulator/demodulator

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2002, Pages 1613-1618

  Wu, Wei ^a   Chin, Shu Shin ^a   Hong, Sangjin ^a  

^a Stony Brook University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEMODULATORS; DIGITAL SIGNAL PROCESSING; ENERGY UTILIZATION; FAST FOURIER TRANSFORMS; FIR FILTERS; MODULATORS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

DATA RATES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038643981     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. C. Dick and F. J. Harris, "Configurable Logic for Digital Communications: Some Signal Processing Perspectives," IEEE Commun. Mag., pp. 107-111, Aug. 1999.
2. E. Grayver and B. Daneshrad, "A Reconfigurable 8 GOP ASIC Architecture for High-Speed Data Communications," IEEE J. Sel. Areas in Commun., vol.18, No. 11, pp. 2161-2171, 2000.
3. J. M. Rabaey, "Reconfigurable Processing: The Solution to Low-Power Programmable DSP," Proc. 1997 ICASSP Conf., Munich, Germany, Apr. 1997.
4. H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous and J. M. Rabaey, "A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Singal Processing," IEEE J. Solid-State Circuits, Vol. 35, No. 11, pp. 1697-1704, 2000.
5. J. Min, H-C. Liu, A. Rofougaran, S. Khorram, H. Samueli and A. A. Abidi, "A Low-Power Correlation Detector For Binary FSK Direct-Conversion Receivers," Electronics Letters 22 June 1995, vol.31, (no.13):1030-2.
6. D. Cohen, "Simplified Control of FFT Hardware," IEEE Trans. Acoust., Speech, Signal Process., vol. 24, pp. 577-579, 1976.
7. Y. T. Ma, "An effective memory addressing scheme for FFT processors," IEEE Trans. Signal Processing, vol. 47, pp. 907-911, 1999.
8. M. Hasan and T. Arslan, " Scheme for reducing size of coefficient memory in FFT processor," Electronics Letters, vol. 38, pp. 163-164, 2002.
9. D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, and C. Ebeling, "Architecture Design of Reconfigurable Pipelined Datapaths", 20th Conf. Advanced Research in VLSI, 1999.
10. A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. M. Rabaey, "Evaluation of a Low-Power Reconfigurable DSP Architecture," Proc. Reconfigurable Architectures Workshop, Orlando, FL, March 1998.