Scheme for reducing size of coefficient memory in FFT processor

Electronics Letters

Volumn 38, Issue 4, 2002, Pages 163-164

  Hasan, Mohammad ^a   Arslan, T ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; FAST FOURIER TRANSFORMS;

COEFFICIENT MEMORY REDUCTION;

MICROPROCESSOR CHIPS;

EID: 0037075215     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020117     Document Type: Article

References (4)

1. Simplified control of FFT hardware
2. Hardware efficient control of memory addressing for high performance FFT processors
3. Efficient FFT implementation using digit-serial arithmetic
4. An effective memory addressing scheme for FFT processors