Process sensitivity and robustness analysis of via-first dual-damascene process

IEEE Transactions on Semiconductor Manufacturing

Volumn 16, Issue 2, 2003, Pages 307-313

  Tsui, Bing Yue ^a   Chen, Chih Wei ^b   Huang, Shien Ming ^b   Lin, Shyue Shyh ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Copper; Dual damascene; Interconnections

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC LINES; ELECTRIC POWER SYSTEM INTERCONNECTION; ETCHING; PROCESS CONTROL; ROBUSTNESS (CONTROL SYSTEMS); SENSITIVITY ANALYSIS;

PROCESS SENSITIVITY;

ULSI CIRCUITS;

EID: 0038630709     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2003.811887     Document Type: Article

References (11)

1. International Technology Roadmap for Semiconductors, Semiconductor Industry Assn., 1999, p. 168.
2. K. Ueno, K. Ohto, K. Tsunernari, K. Kajiyana, K. Kikuta, and T. Kikkawa, "A quarter-micron planarized interconnection technology with self-aligned plug," in IEDM Tech. Dig., 1992, p. 305.
3. K. Kikuta, T. Nakajima, K. Ueno, and Kikkawa, "Multilevel planarized-trench-Aluminum (PTA) interconnection using reflow sputtering and chemical mechanical polishing," in IEDM Tech. Dig., 1993, p. 285.
4. T. Nguyen, B. D. Ulrich, L. R. Allen, and D. R. Evans, "A novel damascene process for one mask via/interconnect formation," in Proc. VLSI Symp., 1996, p. 118.
5. R. D. Tacito and C. Steinbruechel, "Fine-line patterning of parylene-n by reactive ion etching for application as an interlayer dielectric," J. Electrochem. Soc., vol. 143, p. 1974, 1996.
6. P. Singer, "Making the move to dual damascene processing," Semiconduct. Int., p. 79, Aug. 1997.
7. C. Verove, B. Descouts, P. Gayet, M. Guillermet, E. Sabouret, P. Spinelli, and E. Van der Vegt, "Dual damascene architectures evaluation for the 0.18 μm technology and below," in Proc. Int. Interconnect Technology Conf. (IITC), 2000, p. 267.
8. S. S. Lin, C. W. Chen, S. M. Huang, T. K. Kang, C. N. Yeh, T. L. Li, B. Y. Tsui, and C. C. Hsia, "An optimized integration scheme for 0.13 μm technology node dual-damascene Cu interconnect," in Proc. Int. Interconnect Technology Conf. (IITC), 2000, p. 273.
9. R. F. Schnabel, D. Dobuzinsky, J. Gambino, K. P. Muller, F. Wang, and D. C. Perng, "Dry etch challenges of 0.25 μm dual damascene structures," Microelectronics Eng., vol. 37/38, p. 59, 1997.
10. R. Iggulden, L. Clevenger, G. Costrini, D. Dobuzinsky, R. Filippi, J. Gambino, L. Gignac, C. Lin, R. Longo, G. Lu, J. Ning, J. Nuetzel, K. Rodbell, M. Ronay, F. Schnabel, J. Stephens, D. Tobben, and S. Weber, "An advanced 4 level BEOL process with dual damascene Al wiring for 1 Gbit DRAM's," in Proc. VLSI Multilevel Interconnect Conf. (VMIC), 1998, p. 19.
11. A. Blosse, U. Raghuram, S. Thekdi, B. Koutny, G. Lau, S. L. Koh, C. Goodenough, T. Pouedras, A. Sethuraman, S. Geha, T. Chowdhury, S. Guggilla, N. Krishna, J. Su, C. Cha, G. Yao, and J. B. Price, "PVD aluminun dual damascene interconnection: Yield comparision between counterbore and self aligned approaches," in Proc. Int. Interconnect Technology Conf. (IITC), 1999, p. 215.