Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

IEEE Transactions on Semiconductor Manufacturing

Volumn 16, Issue 2, 2003, Pages 319-334

  Ker, Ming Dou ^a   Lo, Wen Yu ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Design rule; Guard ring; I O cell; Latchup; Pickup

Indexed keywords

FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; THERMAL EFFECTS;

LATCHUP PREVENTION;

CMOS INTEGRATED CIRCUITS;

EID: 0038630656     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2003.811885     Document Type: Article

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