Analysis and prevention of DRAM latch-up during power-on

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 1, 1997, Pages 79-85

  Kim, Young Hee ^b,c,d   Sim, Jae Yoon ^a,b,e   Park, Hong June ^{a,b,f,g,h,i,j,k}   Doh, Jae Ik ^c   Park, Kun Woo ^c,g   Chung, Hyun Woong ^c,l   Oh, Jong Hoon ^c,f,m,n,o   Oh, Choon Sik ^c,g,p,q,r   Ahn, Seung Han ^c,s,t  

^a IEEE

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

^d Kyungpook National University   (South Korea)

^e POSTECH VLSI System Laboratory

^f Seoul National University   (South Korea)

^g Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ ETRI Korea   (South Korea)

^j INTEL CORPORATION   (United States)

^k Korean Adv Inst Sci Technol P ^*

^l Chung Ang University   (South Korea)

^m Hyundai Electronics America   (United States)

ⁿ Hyundai Electronics Industries Korea   (South Korea)

^o DRAM Development Projects

^p IBM T J WATSON RESEARCH CENTER   (United States)

^q MOSFET Technology Group

^r Semiconductor Division

^s Yonsei University   (South Korea)

^t OREGON STATE UNIVERSITY   (United States)

more..

Author keywords

CMOS memory integrated circuits; DRAM chips; Integrated circuit reliability; Modeling; Power distribution lines

Indexed keywords

BIPOLAR TRANSISTORS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; LOGIC GATES; SHORT CIRCUIT CURRENTS; SWITCHING FUNCTIONS; TRIGGER CIRCUITS; VOLTAGE MEASUREMENT;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) TRANSMISSION GATE; DATA BUS; DYNAMIC RANDOM ACCESS MEMORY (DRAM); POWER ON LATCH UP PHENOMENON; SOFTWARE PACKAGE HSPICE;

RANDOM ACCESS STORAGE;

EID: 0030782779     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.553181     Document Type: Article

References (10)

1. R. R. Troutman, Latch-up CMOS Technology. Boston: Kluwer, 1986.
2. G. Hu, "A better understanding of CMOS latchup," IEEE Trans. Electron Devices, vol. ED-31, p. 62, Jan. 1984.
3. R. D. Rung, "Trench isolation prospects for application in CMOS VLSI," in IEDM Tech. Dig., 1984, pp. 574-577.
4. R. K. Gupta, I. Sakai, and C. Hu, "Effects of substrate resistance on CMOS latchup holding voltages," IEEE Trans. Electron Devices, vol. ED-34, pp. 2309-2916, Nov. 1987.
5. R. Menozzi et al., "Layout dependence of CMOS latch-up," IEEE Trans. Electron Devices, vol. 35, pp. 1892-1901, Nov. 1988.
6. Y.-H. Yang and C.-Y. Wu, "A new criterion for transient latch-up analysis in bulk CMOS," IEEE Trans. Electron Devices, vol. 36, pp. 1336-1347, July 1989.
7. J. Winnerl and W. Reczek, "Static and transient latch-up hardness in n-well CMOS with on-chip substrate bias generator," in IEDM Tech. Dig., 1985, pp. 504-508.
8. T. Furuyama et al., "A latch-up-like new failure mechanism for high-density CMOS dynamic RAM's," IEEE J. Solid-State Circuits, vol. 25, pp. 42-47, Feb. 1990.
9. D. B. Estreich, "The physics and modeling of latch-up and CMOS integrated circuits," Stanford Univ. Tech. Rep. G-201-9, Nov. 1980.
10. J. Y. Sim, J. S. Kim, K. H. Kim, and H. J. Park, "A global-minimum finding SPICE model parameter extracting program using the fast simulated diffusion algorithm with application to BSIM1, BSIM3, Level 3 and Gummel-Poon models," in Proc. Tech. Dig. Int. Conf. VLSI and CAD, Daejun, Korea, Nov. 1993, pp. 135-138.