Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 267-272

  Ker, Ming Dou ^a   Lo, Wen Yu ^a   Chen, Tung Yang ^a   Tang, Howard ^b   Chen, S S ^b   Wang, M C ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EXTRACTION; SEMICONDUCTING SILICON; SILICIDES;

AREA-EFFICIENT; CORE CIRCUIT; EXPERIMENTAL EXTRACTION; EXPERIMENTAL VERIFICATION; EXTRACTION METHOD; RULE EXTRACTION; SHALLOW TRENCH ISOLATION; TEST PATTERN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0009556831     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915241     Document Type: Conference Paper

References (11)

1. R. R. Troutman, Latchup in CMOS Technology, Kluwer Academie Publishers, 1986.
2. M. Hargrove, et al, "Latchup in CMOS Technology," Proc. of IEEE Int. Reliability Physics Symp., 1998, pp. 269-278.
3. M.-D. Ker and C.-Y. Wu, "Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method: Part I - theoretical derivation," IEEE Trans. on Electron Devices, Vol. 42, pp. 1141-1148, 1995.
4. T. Aoki, "A practical high-latchup immunity design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSI's," IEEE Trans. on Electron Devices, Vol. 40, pp. 1432-1436, 1993.
5. R. Menozzi, et al, "Layout dependence of CMOS latchup," IEEE Trans. on Electron Devices, Vol. 35, pp. 1892-1901, 1988.
6. R. Menozzi, et al, "Effects of the interaction of neighboring structures on the latchup behavior of CMOS IC's," IEEE Trans. on Electron Devices, Vol. 38, pp. 1978-1981, 1991.
7. J. Quincke, "Novel test structure for the investigation of the efficiency of guard rings used for I/O latchup prevention," Proc. of Int. Conf. on Micro. Test Structure, 1990, pp. 35-39.
8. C. Leroux, et al, "Building in reliability with latch-up, ESD and hot carrier effects on 0.25 urn CMOS technology," Microelectronics Reliability, Vol. 38, pp. 1547-1552, 1998.
9. IC Latch-up Test, EIA/JEDEC Standard Nó. 78, Electronic Industries Association, 1997.
10. G. Weiss and D. Young, "Transient-induced latchup testing of CMOS integrated circuits," Proc. of EOS/ESD Symp., 1995, pp. 194-198.
11. Y.-H. Kim, et al, "Analysis and prevention of DRAM latch-up during power-on," IEEE, of Solid-State Circuits, Vol. 32, pp. 79-85, 1997.